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Re: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERF
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field |
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Date: |
Tue, 11 Feb 2020 10:34:36 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/11/20 9:37 AM, Peter Maydell wrote:
> We already define FIELD macros for ID_DFR0, so use them in the
> one place where we're doing direct bit value manipulation.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> We have lots of this non-FIELD style in the code, of course;
> I change this one purely because it otherwise looks a bit odd
> sat next to the ID_AA64DFR0 line that was changed in the previous
> patch...
> ---
> target/arm/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH 02/13] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, (continued)
- [PATCH 02/13] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/11
- [PATCH 01/13] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/11
- [PATCH 03/13] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/11
- [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/11
- [PATCH 05/13] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/11
- [PATCH 09/13] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/11
- [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/11
- [PATCH 04/13] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/11