[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit
|
From: |
Richard Henderson |
|
Subject: |
Re: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit |
|
Date: |
Tue, 11 Feb 2020 10:55:16 -0800 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The LC bit in the PMCR_EL0 register is supposed to be:
> * read/write
> * RES1 on an AArch64-only implementation
> * an architecturally UNKNOWN value on reset
> (and use of LC==0 by software is deprecated).
>
> We were implementing it incorrectly as read-only always zero,
> though we do have all the code needed to test it and behave
> accordingly.
>
> Instead make it a read-write bit which resets to 1 always, which
> satisfies all the architectural requirements above.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/helper.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [PATCH 03/13] target/arm: Define and use any_predinv isar_feature test, (continued)
- [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/11
- [PATCH 05/13] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/11
- [PATCH 09/13] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/11
- [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/11
- [PATCH 04/13] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/11
- [PATCH 10/13] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/11
- [PATCH 07/13] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/11
- [PATCH 08/13] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/11