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[PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus
From: |
Richard Henderson |
Subject: |
[PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus |
Date: |
Fri, 14 Feb 2020 10:15:32 -0800 |
We are going to convert FEATURE tests to ISAR tests,
so FPSP needs to be set for these cpus, like we have
already for FPDP.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f0bd419dd8..92006e56c8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1869,10 +1869,11 @@ static void arm926_initfn(Object *obj)
*/
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
/*
- * Similarly, we need to set MVFR0 fields to enable double precision
- * and short vector support even though ARMv5 doesn't have this register.
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
*/
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
}
@@ -1911,10 +1912,11 @@ static void arm1026_initfn(Object *obj)
*/
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
/*
- * Similarly, we need to set MVFR0 fields to enable double precision
- * and short vector support even though ARMv5 doesn't have this register.
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
*/
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
{
--
2.20.1
- [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2], (continued)
- [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2], Richard Henderson, 2020/02/14
- [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places, Richard Henderson, 2020/02/14
- [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32, Richard Henderson, 2020/02/14
- [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2, Richard Henderson, 2020/02/14
- [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus,
Richard Henderson <=
- [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Richard Henderson, 2020/02/14
- [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16, Richard Henderson, 2020/02/14
- [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Richard Henderson, 2020/02/14
- [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Richard Henderson, 2020/02/14
- [PATCH 08/19] target/arm: Perform fpdp_v2 check first, Richard Henderson, 2020/02/14