[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_
From: |
Richard Henderson |
Subject: |
[PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} |
Date: |
Fri, 14 Feb 2020 10:15:35 -0800 |
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5f08cbd2d8..4ff28418df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3429,12 +3429,30 @@ static inline bool isar_feature_aa32_fpshvec(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv2 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
+}
+
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
+}
+
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
--
2.20.1
- Re: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2], (continued)
- [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places, Richard Henderson, 2020/02/14
- [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32, Richard Henderson, 2020/02/14
- [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2, Richard Henderson, 2020/02/14
- [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus, Richard Henderson, 2020/02/14
- [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3},
Richard Henderson <=
- [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16, Richard Henderson, 2020/02/14
- [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Richard Henderson, 2020/02/14
- [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Richard Henderson, 2020/02/14
- [PATCH 08/19] target/arm: Perform fpdp_v2 check first, Richard Henderson, 2020/02/14
- [PATCH 10/19] target/arm: Add missing checks for fpsp_v2, Richard Henderson, 2020/02/14