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[PULL 11/52] target/arm: Fix select for aa64_va_parameters_both
From: |
Peter Maydell |
Subject: |
[PULL 11/52] target/arm: Fix select for aa64_va_parameters_both |
Date: |
Fri, 21 Feb 2020 13:06:59 +0000 |
From: Richard Henderson <address@hidden>
Select should always be 0 for a regime with one range.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 46 +++++++++++++++++++++++----------------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 366dbcf460d..b09a5012841 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10241,13 +10241,8 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState
*env, uint64_t va,
bool tbi, tbid, epd, hpd, using16k, using64k;
int select, tsz;
- /*
- * Bit 55 is always between the two regions, and is canonical for
- * determining if address tagging is enabled.
- */
- select = extract64(va, 55, 1);
-
if (!regime_has_2_ranges(mmu_idx)) {
+ select = 0;
tsz = extract32(tcr, 0, 6);
using64k = extract32(tcr, 14, 1);
using16k = extract32(tcr, 15, 1);
@@ -10260,23 +10255,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState
*env, uint64_t va,
tbid = extract32(tcr, 29, 1);
}
epd = false;
- } else if (!select) {
- tsz = extract32(tcr, 0, 6);
- epd = extract32(tcr, 7, 1);
- using64k = extract32(tcr, 14, 1);
- using16k = extract32(tcr, 15, 1);
- tbi = extract64(tcr, 37, 1);
- hpd = extract64(tcr, 41, 1);
- tbid = extract64(tcr, 51, 1);
} else {
- int tg = extract32(tcr, 30, 2);
- using16k = tg == 1;
- using64k = tg == 3;
- tsz = extract32(tcr, 16, 6);
- epd = extract32(tcr, 23, 1);
- tbi = extract64(tcr, 38, 1);
- hpd = extract64(tcr, 42, 1);
- tbid = extract64(tcr, 52, 1);
+ /*
+ * Bit 55 is always between the two regions, and is canonical for
+ * determining if address tagging is enabled.
+ */
+ select = extract64(va, 55, 1);
+ if (!select) {
+ tsz = extract32(tcr, 0, 6);
+ epd = extract32(tcr, 7, 1);
+ using64k = extract32(tcr, 14, 1);
+ using16k = extract32(tcr, 15, 1);
+ tbi = extract64(tcr, 37, 1);
+ hpd = extract64(tcr, 41, 1);
+ tbid = extract64(tcr, 51, 1);
+ } else {
+ int tg = extract32(tcr, 30, 2);
+ using16k = tg == 1;
+ using64k = tg == 3;
+ tsz = extract32(tcr, 16, 6);
+ epd = extract32(tcr, 23, 1);
+ tbi = extract64(tcr, 38, 1);
+ hpd = extract64(tcr, 42, 1);
+ tbid = extract64(tcr, 52, 1);
+ }
}
tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
--
2.20.1
- [PULL 00/52] target-arm queue, Peter Maydell, 2020/02/21
- [PULL 01/52] aspeed/scu: Create separate write callbacks, Peter Maydell, 2020/02/21
- [PULL 02/52] aspeed/scu: Implement chip ID register, Peter Maydell, 2020/02/21
- [PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register, Peter Maydell, 2020/02/21
- [PULL 04/52] mainstone: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 05/52] z2: Make providing flash images non-mandatory, Peter Maydell, 2020/02/21
- [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT, Peter Maydell, 2020/02/21
- [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX, Peter Maydell, 2020/02/21
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth, Peter Maydell, 2020/02/21
- [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both,
Peter Maydell <=
- [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Peter Maydell, 2020/02/21
- [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS, Peter Maydell, 2020/02/21
- [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae, Peter Maydell, 2020/02/21
- [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/21
- [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid, Peter Maydell, 2020/02/21
- [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/21
- [PULL 17/52] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/21
- [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/21
- [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/21
- [PULL 18/52] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/21