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[PULL 17/52] target/arm: Define and use any_predinv isar_feature test
From: |
Peter Maydell |
Subject: |
[PULL 17/52] target/arm: Define and use any_predinv isar_feature test |
Date: |
Fri, 21 Feb 2020 13:07:05 +0000 |
Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv",
define and use an any_predinv isar_feature test function.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 5 +++++
target/arm/helper.c | 9 +--------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7ccd65bdce3..ef0feb228ab 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3677,6 +3677,11 @@ static inline bool isar_feature_any_fp16(const
ARMISARegisters *id)
return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
}
+static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ad2bfa9ef83..ab36f33b719 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7721,14 +7721,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
#endif /*CONFIG_USER_ONLY*/
#endif
- /*
- * While all v8.0 cpus support aarch64, QEMU does have configurations
- * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
- * which will set ID_ISAR6.
- */
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
- ? cpu_isar_feature(aa64_predinv, cpu)
- : cpu_isar_feature(aa32_predinv, cpu)) {
+ if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
}
--
2.20.1
- [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT, (continued)
- [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT, Peter Maydell, 2020/02/21
- [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX, Peter Maydell, 2020/02/21
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth, Peter Maydell, 2020/02/21
- [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both, Peter Maydell, 2020/02/21
- [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Peter Maydell, 2020/02/21
- [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS, Peter Maydell, 2020/02/21
- [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae, Peter Maydell, 2020/02/21
- [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/21
- [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid, Peter Maydell, 2020/02/21
- [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/21
- [PULL 17/52] target/arm: Define and use any_predinv isar_feature test,
Peter Maydell <=
- [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/21
- [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/21
- [PULL 18/52] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/21
- [PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/21
- [PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/21
- [PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/21
- [PULL 23/52] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/21
- [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/21
- [PULL 26/52] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/21
- [PULL 25/52] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/21