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[PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v
From: |
Peter Maydell |
Subject: |
[PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} |
Date: |
Fri, 21 Feb 2020 13:07:37 +0000 |
From: Richard Henderson <address@hidden>
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1e2aae276bf..a7fc86c23cf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3467,12 +3467,30 @@ static inline bool isar_feature_aa32_fpshvec(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv2 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
+}
+
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
+}
+
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
--
2.20.1
- [PULL 37/52] arm: allwinner: Wire up USB ports, (continued)
- [PULL 37/52] arm: allwinner: Wire up USB ports, Peter Maydell, 2020/02/21
- [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property, Peter Maydell, 2020/02/21
- [PULL 39/52] target/arm: Convert PMUL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd, Peter Maydell, 2020/02/21
- [PULL 40/52] target/arm: Convert PMULL.64 to gvec, Peter Maydell, 2020/02/21
- [PULL 38/52] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2020/02/21
- [PULL 41/52] target/arm: Convert PMULL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32, Peter Maydell, 2020/02/21
- [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places, Peter Maydell, 2020/02/21
- [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus, Peter Maydell, 2020/02/21
- [PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3},
Peter Maydell <=
- [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2, Peter Maydell, 2020/02/21
- [PULL 43/52] sh4: Fix PCI ISA IO memory subregion, Peter Maydell, 2020/02/21
- [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16, Peter Maydell, 2020/02/21
- [PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/21
- [PULL 50/52] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/21
- [PULL 52/52] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21