On Fri, Feb 21, 2020, 17:50 Dr. David Alan Gilbert <
address@hidden> wrote:
* Stefan Hajnoczi (address@hidden) wrote:
> On Fri, Feb 21, 2020 at 3:36 PM Andrzej Jakowski
> <address@hidden> wrote:
> > On 2/21/20 6:45 AM, Stefan Hajnoczi wrote:
> > > Why is msync(2) done on memory loads instead of stores?
> >
> > This is my interpretation of NVMe spec wording with regards to PMRWBM field
> > which says:
> >
> > "The completion of a memory read from any Persistent
> > Memory Region address ensures that all prior writes to the
> > Persistent Memory Region have completed and are
> > persistent."
>
> Thanks, I haven't read the PMR section of the spec :).
>
> A synchronous operation is bad for virtualization performance. While
> the sync may be a cheap operation in hardware, it can be arbitrarily
> expensive with msync(2). The vCPU will be stuck until msync(2)
> completes on the host.
>
> It's also a strange design choice since performance will suffer when
> an unrelated read has to wait for writes to complete. This is
> especially problematic for multi-threaded applications or multi-core
> systems where I guess this case is hit frequently. Maybe it's so
> cheap in hardware that it doesn't matter? But then why didn't NVDIMM
> use this mechanism?
>
> If anyone knows the answer I'd be interested in learning. But this
> isn't a criticism of the patch - of course it needs to implement the
> hardware spec and we can't change it.
Is this coming from the underlying PCIe spec ?
In PCIe Base 4.0 Rev 0.3 Feb19-2014, section 2.4.1 Transaction ordering,
there's a Table 2-39 and entry B2a in that table is:
'A Read Request must not pass a Posted Request unless B2b applies.'
and a posted request is defined as a 'Memory Write Request or a Message
Request'.
???
No, that relates to transaction ordering in PCI, not data persistence in PMR. PMR can define whatever persistence semantics it wants.
The completion of the write transaction at the PCI level does not mean data has to be persistent at the PMR level.
Stefan