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From: | Jim Wilson |
Subject: | Re: [PATCH v5 4/4] target/riscv: add vector configure instruction |
Date: | Wed, 26 Feb 2020 12:20:28 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/21/20 1:45 AM, LIU Zhiwei wrote:
+ /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ + if (a->rs1 == 0) { + /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ + s1 = tcg_const_tl(RV_VLEN_MAX);
This is wrong for the current draft of the vector spec. x0 now means don't change VL. So this needs to be version specific.
Jim
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