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[PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2
From: |
Peter Maydell |
Subject: |
[PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 |
Date: |
Fri, 28 Feb 2020 16:38:15 +0000 |
From: Richard Henderson <address@hidden>
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce another
feature tests for VFPv3.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 4 ++--
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a128d48d405..1e6eac0cd2a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
- /* Return true if CPU supports double precision floating point */
+ /* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba46e2557a1..e94876c30ca 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM
*a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn
*fn,
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn
*fn, int vd, int vm)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s,
arg_VCVT_dp_int *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
--
2.20.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2020/02/28
- [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port, Peter Maydell, 2020/02/28
- [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, Peter Maydell, 2020/02/28
- [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller, Peter Maydell, 2020/02/28
- [PULL 04/33] arm_gic: Mask the un-supported priority bits, Peter Maydell, 2020/02/28
- [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2,
Peter Maydell <=
- [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4, Peter Maydell, 2020/02/28
- [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd, Peter Maydell, 2020/02/28
- [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/28
- [PULL 11/33] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/28
- [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/28
- [PULL 13/33] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/28
- [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac, Peter Maydell, 2020/02/28
- [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Peter Maydell, 2020/02/28
- [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode, Peter Maydell, 2020/02/28
- [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class, Peter Maydell, 2020/02/28