[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32
From: |
Peter Maydell |
Subject: |
[PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac |
Date: |
Fri, 28 Feb 2020 16:38:21 +0000 |
From: Richard Henderson <address@hidden>
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 12 ++++++++++++
target/arm/cpu.c | 6 +++++-
target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++----
target/arm/translate.c | 2 +-
4 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b94d2a5ace4..b29b0eddfc3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
+/*
+ * Note that this ID register field covers both VFP and Neon FMAC,
+ * so should usually be tested in combination with some other
+ * check that confirms the presence of whichever of VFP or Neon is
+ * relevant, to avoid accidentally enabling a Neon feature on
+ * a VFP-no-Neon core or vice-versa.
+ */
+static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
+}
+
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5be4c258096..dc45865c7a7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1512,7 +1512,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
- u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
cpu->isar.mvfr1 = u;
u = cpu->isar.mvfr2;
@@ -1535,6 +1534,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
cpu->isar.mvfr0 = u;
+
+ /* Despite the name, this field covers both VFP and Neon */
+ u = cpu->isar.mvfr1;
+ u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
+ cpu->isar.mvfr1 = u;
}
if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index f88a95438fc..03ba8d7aac0 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
@@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 79880adaad2..0489e0cdaa6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
}
break;
case NEON_3R_VFM_VQRDMLSH:
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
return 1;
}
break;
--
2.20.1
- [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, (continued)
- [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, Peter Maydell, 2020/02/28
- [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller, Peter Maydell, 2020/02/28
- [PULL 04/33] arm_gic: Mask the un-supported priority bits, Peter Maydell, 2020/02/28
- [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2, Peter Maydell, 2020/02/28
- [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4, Peter Maydell, 2020/02/28
- [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd, Peter Maydell, 2020/02/28
- [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/28
- [PULL 11/33] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/28
- [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/28
- [PULL 13/33] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/28
- [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac,
Peter Maydell <=
- [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Peter Maydell, 2020/02/28
- [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode, Peter Maydell, 2020/02/28
- [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class, Peter Maydell, 2020/02/28
- [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0, Peter Maydell, 2020/02/28
- [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp, Peter Maydell, 2020/02/28
- [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP, Peter Maydell, 2020/02/28
- [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation, Peter Maydell, 2020/02/28
- [PULL 30/33] target/arm: Implement v8.3-RCPC, Peter Maydell, 2020/02/28
- [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5, Peter Maydell, 2020/02/28
- [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns, Peter Maydell, 2020/02/28