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[PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa3
From: |
Peter Maydell |
Subject: |
[PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp |
Date: |
Fri, 28 Feb 2020 16:38:17 +0000 |
From: Richard Henderson <address@hidden>
We cannot easily create "any" functions for these, because the
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
Which means that an aarch32-only cpu will return incorrect results
when testing the aarch64 registers.
To use these, we must either have context or additionally test
vs ARM_FEATURE_AARCH64.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 11 +++++++++++
target/arm/cpu.c | 9 ++++++---
target/arm/machine.c | 5 +++--
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f7a90f512e3..b94d2a5ace4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
}
+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
+{
+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
@@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
}
+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
+{
+ /* We always set the AdvSIMD and FP fields identically. */
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
+}
+
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be4c2a1253d..5be4c258096 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj)
* KVM does not currently allow us to lie to the guest about its
* ID/feature registers, so the guest always sees what the host has.
*/
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp, cpu)) {
cpu->has_vfp = true;
if (!kvm_enabled()) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
@@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
* We rely on no XScale CPU having VFP so we can use the same bits in the
* TB flags field for VECSTRIDE and XSCALE_CPAR.
*/
- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
- arm_feature(env, ARM_FEATURE_XSCALE)));
+ assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
+ !cpu_isar_feature(aa32_vfp_simd, cpu) ||
+ !arm_feature(env, ARM_FEATURE_XSCALE));
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_M) &&
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 241890ac8cf..c5a2114f51c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -9,9 +9,10 @@
static bool vfp_needed(void *opaque)
{
ARMCPU *cpu = opaque;
- CPUARMState *env = &cpu->env;
- return arm_feature(env, ARM_FEATURE_VFP);
+ return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp_simd, cpu));
}
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
--
2.20.1
- [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd, (continued)
- [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd, Peter Maydell, 2020/02/28
- [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/28
- [PULL 11/33] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/28
- [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/28
- [PULL 13/33] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/28
- [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac, Peter Maydell, 2020/02/28
- [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Peter Maydell, 2020/02/28
- [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode, Peter Maydell, 2020/02/28
- [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class, Peter Maydell, 2020/02/28
- [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0, Peter Maydell, 2020/02/28
- [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp,
Peter Maydell <=
- [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP, Peter Maydell, 2020/02/28
- [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation, Peter Maydell, 2020/02/28
- [PULL 30/33] target/arm: Implement v8.3-RCPC, Peter Maydell, 2020/02/28
- [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5, Peter Maydell, 2020/02/28
- [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns, Peter Maydell, 2020/02/28
- [PULL 22/33] target/arm: Split VMINMAXNM decode, Peter Maydell, 2020/02/28
- [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines, Peter Maydell, 2020/02/28
- [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine, Peter Maydell, 2020/02/28
- [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa, Peter Maydell, 2020/02/28
- [PULL 21/33] target/arm: Split VFM decode, Peter Maydell, 2020/02/28