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[RFC PATCH v2 33/67] Hexagon instruction classes
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v2 33/67] Hexagon instruction classes |
Date: |
Fri, 28 Feb 2020 10:43:29 -0600 |
Used to determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson <address@hidden>
---
target/hexagon/iclass.h | 46 +++++++++++++++++++++
target/hexagon/iclass.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 153 insertions(+)
create mode 100644 target/hexagon/iclass.h
create mode 100644 target/hexagon/iclass.c
diff --git a/target/hexagon/iclass.h b/target/hexagon/iclass.h
new file mode 100644
index 0000000..89288ac
--- /dev/null
+++ b/target/hexagon/iclass.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_ICLASS_H
+#define HEXAGON_ICLASS_H
+
+#include "opcodes.h"
+
+#define ICLASS_FROM_TYPE(TYPE) ICLASS_##TYPE
+
+typedef enum {
+
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE),
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) /* nothing */
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE),
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) /* nothing */
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+
+ ICLASS_FROM_TYPE(COPROC_VX),
+ ICLASS_FROM_TYPE(COPROC_VMEM),
+ NUM_ICLASSES
+} iclass_t;
+
+extern const char *find_iclass_slots(opcode_t opcode, int itype);
+
+#endif
diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c
new file mode 100644
index 0000000..9ada8cd
--- /dev/null
+++ b/target/hexagon/iclass.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "iclass.h"
+
+typedef struct {
+ const char * const slots;
+} iclass_info_t;
+
+static const iclass_info_t iclass_info[] = {
+
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) /* nothing */
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) \
+ [ICLASS_FROM_TYPE(TYPE)] = { .slots = #SLOTS },
+
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) /* nothing */
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) \
+ [ICLASS_FROM_TYPE(TYPE)] = { .slots = #SLOTS },
+
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+
+ {0}
+};
+
+const char *find_iclass_slots(opcode_t opcode, int itype)
+{
+ /* There are some exceptions to what the iclass dictates */
+ if (GET_ATTRIB(opcode, A_ICOP)) {
+ return "2";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT0ONLY)) {
+ return "0";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT1ONLY)) {
+ return "1";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) {
+ return "2";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT3ONLY)) {
+ return "3";
+ } else if (GET_ATTRIB(opcode, A_COF) &&
+ GET_ATTRIB(opcode, A_INDIRECT) &&
+ !GET_ATTRIB(opcode, A_MEMLIKE) &&
+ !GET_ATTRIB(opcode, A_MEMLIKE_PACKET_RULES)) {
+ return "2";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) {
+ return "0";
+ } else if ((opcode == J2_trap0) || (opcode == J2_trap1) ||
+ (opcode == Y2_isync) || (opcode == J2_rte) ||
+ (opcode == J2_pause) || (opcode == J4_hintjumpr)) {
+ return "2";
+ } else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) {
+ return "01";
+ } else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) {
+ return "01";
+ } else if (GET_ATTRIB(opcode, A_CRSLOT23)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_PREFERSLOT0)) {
+ return "0";
+ } else if (GET_ATTRIB(opcode, A_SUBINSN)) {
+ return "01";
+ } else if (GET_ATTRIB(opcode, A_CALL)) {
+ return "23";
+ } else if ((opcode == J4_jumpseti) || (opcode == J4_jumpsetr)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_EXTENSION) && GET_ATTRIB(opcode, A_CVI)) {
+ /* CVI EXTENSIONS */
+ if (GET_ATTRIB(opcode, A_CVI_VM)) {
+ return "01";
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) {
+ return "2";
+ } else if (GET_ATTRIB(opcode, A_CVI_SLOT23)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_CVI_VX)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_CVI_VX_DV)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_CVI_VS_VX)) {
+ return "23";
+ } else if (GET_ATTRIB(opcode, A_MEMLIKE)) {
+ return "01";
+ } else {
+ return "0123";
+ }
+ } else {
+ return iclass_info[itype].slots;
+ }
+}
+
--
2.7.4
- [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers, (continued)
- [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 13/67] Hexagon register map, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 02/67] Hexagon README, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 44/67] Hexagon TCG generation - step 06, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 31/67] Hexagon macros to interface with the generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 14/67] Hexagon instruction/packet decode, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 33/67] Hexagon instruction classes,
Taylor Simpson <=
- [RFC PATCH v2 41/67] Hexagon TCG generation - step 03, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 59/67] Hexagon HVX semantics generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 06/67] Hexagon Disassembler, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 47/67] Hexagon TCG generation - step 09, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics, Taylor Simpson, 2020/02/28