[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH v2 48/67] Hexagon TCG generation - step 10
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v2 48/67] Hexagon TCG generation - step 10 |
Date: |
Fri, 28 Feb 2020 10:43:44 -0600 |
Override compound compare and jump instructions
Signed-off-by: Taylor Simpson <address@hidden>
---
target/hexagon/helper_overrides.h | 105 ++++++++++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 5443a94e..d3311be 100644
--- a/target/hexagon/helper_overrides.h
+++ b/target/hexagon/helper_overrides.h
@@ -1327,4 +1327,109 @@
#define fWRAP_J2_endloop1(GENHLPR, SHORTCODE) \
gen_endloop1()
+/*
+ * Compound compare and jump instructions
+ * Here is a primer to understand the tag names
+ *
+ * Comparison
+ * cmpeqi compare equal to an immediate
+ * cmpgti compare greater than an immediate
+ * cmpgtiu compare greater than an unsigned immediate
+ * cmpeqn1 compare equal to negative 1
+ * cmpgtn1 compare greater than negative 1
+ * cmpeq compare equal (two registers)
+ *
+ * Condition
+ * tp0 p0 is true p0 = cmp.eq(r0,#5); if (p0.new) jump:nt address
+ * fp0 p0 is false p0 = cmp.eq(r0,#5); if (!p0.new) jump:nt
address
+ * tp1 p1 is true p1 = cmp.eq(r0,#5); if (p1.new) jump:nt address
+ * fp1 p1 is false p1 = cmp.eq(r0,#5); if (!p1.new) jump:nt
address
+ *
+ * Prediction (not modelled in qemu)
+ * _nt not taken
+ * _t taken
+ */
+#define fWRAP_J4_cmpeqi_tp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_EQ, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_fp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_EQ, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_EQ, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_fp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_EQ, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_tp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_EQ, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_fp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_EQ, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_tp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_EQ, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqi_fp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_EQ, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_tp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GT, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_fp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GT, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GT, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_fp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GT, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_tp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GT, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_fp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GT, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_tp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GT, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgti_fp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GT, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_tp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GTU, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_fp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GTU, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GTU, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_fp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(0, TCG_COND_GTU, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_tp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GTU, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_fp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GTU, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_tp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GTU, true, RsV, UiV, riV)
+#define fWRAP_J4_cmpgtui_fp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmpi_jmp(1, TCG_COND_GTU, false, RsV, UiV, riV)
+#define fWRAP_J4_cmpeqn1_tp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_EQ, true, RsV, riV)
+#define fWRAP_J4_cmpeqn1_fp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_EQ, false, RsV, riV)
+#define fWRAP_J4_cmpeqn1_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_EQ, true, RsV, riV)
+#define fWRAP_J4_cmpeqn1_fp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_EQ, false, RsV, riV)
+#define fWRAP_J4_cmpeqn1_tp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_EQ, true, RsV, riV)
+#define fWRAP_J4_cmpeqn1_fp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_EQ, false, RsV, riV)
+#define fWRAP_J4_cmpeqn1_tp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_EQ, true, RsV, riV)
+#define fWRAP_J4_cmpeqn1_fp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_EQ, false, RsV, riV)
+#define fWRAP_J4_cmpgtn1_tp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_GT, true, RsV, riV)
+#define fWRAP_J4_cmpgtn1_fp0_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_GT, false, RsV, riV)
+#define fWRAP_J4_cmpgtn1_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_GT, true, RsV, riV)
+#define fWRAP_J4_cmpgtn1_fp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(0, TCG_COND_GT, false, RsV, riV)
+#define fWRAP_J4_cmpgtn1_tp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_GT, true, RsV, riV)
+#define fWRAP_J4_cmpgtn1_fp1_jump_nt(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_GT, false, RsV, riV)
+#define fWRAP_J4_cmpgtn1_tp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_GT, true, RsV, riV)
+#define fWRAP_J4_cmpgtn1_fp1_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_n1_jmp(1, TCG_COND_GT, false, RsV, riV)
+#define fWRAP_J4_cmpeq_tp0_jump_t(GENHLPR, SHORTCODE) \
+ gen_cmpnd_cmp_jmp(0, TCG_COND_EQ, true, RsV, RtV, riV)
+
#endif
--
2.7.4
- [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions, (continued)
- [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 59/67] Hexagon HVX semantics generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 06/67] Hexagon Disassembler, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 47/67] Hexagon TCG generation - step 09, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 48/67] Hexagon TCG generation - step 10,
Taylor Simpson <=
- [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 58/67] Hexagon HVX import macro definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 60/67] Hexagon HVX instruction decoding, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 39/67] Hexagon TCG generation - step 01, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 52/67] Hexagon Linux user emulation, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 46/67] Hexagon TCG generation - step 08, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 30/67] Hexagon opcode data structures, Taylor Simpson, 2020/02/28