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[RFC v2 06/76] target/riscv: fix vill bit index in vtype register
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From: |
frank . chang |
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Subject: |
[RFC v2 06/76] target/riscv: fix vill bit index in vtype register |
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Date: |
Wed, 22 Jul 2020 17:15:29 +0800 |
From: Frank Chang <frank.chang@sifive.com>
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 378f6e82bf..27ce075e50 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
--
2.17.1
- [RFC v2 00/76] target/riscv: support vector extension v0.9, frank . chang, 2020/07/22
- [RFC v2 01/76] target/riscv: drop vector 0.7.1 support, frank . chang, 2020/07/22
- [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9, frank . chang, 2020/07/22
- [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/22
- [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/22
- [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/22
- [RFC v2 06/76] target/riscv: fix vill bit index in vtype register,
frank . chang <=
- [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/07/22
- [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
- [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
- [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
- [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22