Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field

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Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field

From:	Richard Henderson
Subject:	Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field
Date:	Wed, 22 Jul 2020 09:34:48 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, (continued)
- [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/22
  - Re: [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, Richard Henderson, 2020/07/22
- [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/22
- [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/22
- [RFC v2 06/76] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/22
- [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/07/22
  - Re: [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, Richard Henderson, 2020/07/22
- [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
  - Re: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, Richard Henderson, 2020/07/22
- [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
  - Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, Richard Henderson <=
- [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
  - Re: [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, Richard Henderson, 2020/07/22
- [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22
  - Re: [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, Richard Henderson, 2020/07/22
- [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/22
  - Re: [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, Richard Henderson, 2020/07/22
- [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/22
  - Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, Richard Henderson, 2020/07/22
- [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/22
  - Re: [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, Richard Henderson, 2020/07/22

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