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[RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper
From: |
frank . chang |
Subject: |
[RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function |
Date: |
Thu, 6 Aug 2020 18:47:04 +0800 |
From: Frank Chang <frank.chang@sifive.com>
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 5 +++++
target/riscv/helper.h | 1 +
target/riscv/internals.h | 1 +
target/riscv/translate.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 92e076c6ed8..a01b8eab0b3 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
+void helper_set_rod_rounding_mode(CPURISCVState *env)
+{
+ set_float_rounding_mode(float_round_to_odd, &env->fp_status);
+}
+
static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
uint64_t rs3, int flags)
{
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7539b4a5004..b128610978d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 97f023361a9..785fa211955 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -45,6 +45,7 @@ enum {
FRM_RUP = 3, /* Round Up */
FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
FRM_DYN = 7, /* Dynamic rounding mode */
+ FRM_ROD = 8, /* Round to Odd */
};
static inline uint64_t nanbox_s(float32 f)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3869389fe02..e1811c19792 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "instmap.h"
+#include "internals.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
@@ -573,6 +574,10 @@ static void gen_set_rm(DisasContext *ctx, int rm)
return;
}
ctx->frm = rm;
+ if (rm == FRM_ROD) {
+ gen_helper_set_rod_rounding_mode(cpu_env);
+ return;
+ }
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
--
2.17.1
- [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, (continued)
- [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2020/08/06
- [RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2020/08/06
- [RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2020/08/06
- [RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/08/06
- [RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/08/06
- [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2020/08/06
- [RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/08/06
- [RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2020/08/06
- [RFC v3 64/71] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2020/08/06
- [RFC v3 65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/08/06
- [RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function,
frank . chang <=
- [RFC v3 66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/08/06
- [RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/08/06
- [RFC v3 69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/08/06
- [RFC v3 70/71] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/08/06
- [RFC v3 71/71] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/08/06