[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 06/20] target/riscv: Clean up fmv.w.x
|
From: |
Alistair Francis |
|
Subject: |
[PULL 06/20] target/riscv: Clean up fmv.w.x |
|
Date: |
Wed, 12 Aug 2020 15:30:31 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvf.inc.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index f9a9e0643a..0d04677a02 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
+ tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
--
2.27.0
[PULL 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Alistair Francis, 2020/08/12
[PULL 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/12
[PULL 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/12
[PULL 06/20] target/riscv: Clean up fmv.w.x,
Alistair Francis <=
[PULL 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/12
[PULL 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/12
[PULL 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/12
[PULL 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/12
[PULL 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/12
[PULL 16/20] target/riscv: Fix the translation of physical address, Alistair Francis, 2020/08/12
[PULL 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/12
[PULL 17/20] target/riscv: Change the TLB page size depends on PMP entries., Alistair Francis, 2020/08/12
[PULL 13/20] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u, Alistair Francis, 2020/08/12
[PULL 18/20] hw/intc: ibex_plic: Update the pending irqs, Alistair Francis, 2020/08/12