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Re: [PULL 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c
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From: |
Richard Henderson |
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Subject: |
Re: [PULL 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c |
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Date: |
Thu, 13 Aug 2020 09:48:52 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/13/20 7:46 AM, Alistair Francis wrote:
>> Hi Alistair,
>>
>> As Chih-Min said, it's wrong here. He has given the correct patch code
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg728540.html
>>
>> We can either squash the code to this patch or add an separate patch
>> later. I prefer the former.
>> Thanks very much.
>
> Richard are you ok if I squash this diff into the patch and send a PR v2?
>
> diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
> b/target/riscv/insn_trans/trans_rvf.inc.c
> index f9a9e0643a..76f281d275 100644
> --- a/target/riscv/insn_trans/trans_rvf.inc.c
> +++ b/target/riscv/insn_trans/trans_rvf.inc.c
> @@ -201,7 +201,8 @@ static bool trans_fsgnjn_s(DisasContext *ctx,
> arg_fsgnjn_s *a)
> * This formulation retains the nanboxing of rs1.
> */
> mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1));
> - tcg_gen_andc_i64(rs2, mask, rs2);
> + tcg_gen_not_i64(rs2, rs2); // forget to inverse rs2
> + tcg_gen_andc_i64(rs2, rs2, mask); //mask needs to be
Ah, well. Yes, it's a bug. However,
~rs2 & ~mask
= ~(rs2 | mask)
so a better fix could be
- tcg_gen_andc_i64(rs2, mask, rs2);
+ tcg_gen_nor_i64(rs2, rs2, mask);
As an aside, I think perhaps I should have added a ppc-style rotate-and-insert
primitive to handle this sort of bitfield insert, since the best set of host
insns to perform this operation, when the start of the field is not bit 0, is
difficult to predict from the translator.
r~
[PULL 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Alistair Francis, 2020/08/12
[PULL 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/12
[PULL 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/12
[PULL 06/20] target/riscv: Clean up fmv.w.x, Alistair Francis, 2020/08/12
[PULL 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/12
[PULL 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/12
[PULL 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/12
[PULL 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/12
[PULL 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/12