Re: [PATCH 00/20] target/arm: SVE2 preparatory patches

[no-reply]

Patchew URL: 
20200815013145.539409-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20200815013145.539409-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20200815013145.539409-1-richard.henderson@linaro.org
Subject: [PATCH 00/20] target/arm: SVE2 preparatory patches

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200812183250.9221-1-cfontana@suse.de -> 
patchew/20200812183250.9221-1-cfontana@suse.de
 - [tag update]      patchew/20200814082841.27000-1-f4bug@amsat.org -> 
patchew/20200814082841.27000-1-f4bug@amsat.org
 * [new tag]         
patchew/20200815013145.539409-1-richard.henderson@linaro.org -> 
patchew/20200815013145.539409-1-richard.henderson@linaro.org
Switched to a new branch 'test'
ee9e70c target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
68d3120 target/arm: Convert integer multiply-add (indexed) to gvec for aa64 
advsimd
4915d69 target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
4ede158 target/arm: Fix sve_punpk_p vs odd vector lengths
94aae8d target/arm: Fix sve_zip_p vs odd vector lengths
dd7dc33 target/arm: Fix sve_uzp_p vs odd vector lengths
b32338b target/arm: Generalize inl_qrdmlah_* helper functions
095ea16 target/arm: Tidy SVE tszimm shift formats
e34d62c target/arm: Split out gen_gvec_ool_zz
c0d82b9 target/arm: Split out gen_gvec_ool_zzz
a99dbac target/arm: Split out gen_gvec_ool_zzp
cfb28d1 target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
0592c7a target/arm: Split out gen_gvec_ool_zzzp
6e5fc25 target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
05415f2 target/arm: Clean up 4-operand predicate expansion
7adbccc target/arm: Merge do_vector2_p into do_mov_p
c7cd875 target/arm: Rearrange {sve,fp}_check_access assert
a86390b target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
289f152 target/arm: Split out gen_gvec_fn_zz
4bbc96a qemu/int128: Add int128_lshift

=== OUTPUT BEGIN ===
1/20 Checking commit 4bbc96a0e6a5 (qemu/int128: Add int128_lshift)
2/20 Checking commit 289f152a8194 (target/arm: Split out gen_gvec_fn_zz)
3/20 Checking commit a86390b7a972 (target/arm: Split out gen_gvec_fn_zzz, 
do_zzz_fn)
4/20 Checking commit c7cd87586c88 (target/arm: Rearrange {sve,fp}_check_access 
assert)
5/20 Checking commit 7adbccc844ea (target/arm: Merge do_vector2_p into do_mov_p)
6/20 Checking commit 05415f287adb (target/arm: Clean up 4-operand predicate 
expansion)
7/20 Checking commit 6e5fc25bd7b0 (target/arm: Use tcg_gen_gvec_bitsel for 
trans_SEL_pppp)
8/20 Checking commit 0592c7a7e8a5 (target/arm: Split out gen_gvec_ool_zzzp)
9/20 Checking commit cfb28d174ae5 (target/arm: Merge helper_sve_clr_* and 
helper_sve_movz_*)
10/20 Checking commit a99dbace62f6 (target/arm: Split out gen_gvec_ool_zzp)
11/20 Checking commit c0d82b9048d4 (target/arm: Split out gen_gvec_ool_zzz)
12/20 Checking commit e34d62ca031f (target/arm: Split out gen_gvec_ool_zz)
13/20 Checking commit 095ea164e906 (target/arm: Tidy SVE tszimm shift formats)
14/20 Checking commit b32338b23247 (target/arm: Generalize inl_qrdmlah_* helper 
functions)
15/20 Checking commit dd7dc33f523b (target/arm: Fix sve_uzp_p vs odd vector 
lengths)
16/20 Checking commit 94aae8d657bb (target/arm: Fix sve_zip_p vs odd vector 
lengths)
17/20 Checking commit 4ede158d452e (target/arm: Fix sve_punpk_p vs odd vector 
lengths)
18/20 Checking commit 4915d696b4a9 (target/arm: Convert integer multiply 
(indexed) to gvec for aa64 advsimd)
ERROR: space prohibited before that close parenthesis ')'
#76: FILE: target/arm/vec_helper.c:730:
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )

ERROR: space prohibited before that close parenthesis ')'
#93: FILE: target/arm/vec_helper.c:751:
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )

total: 2 errors, 0 warnings, 74 lines checked

Patch 18/20 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

19/20 Checking commit 68d3120b2c82 (target/arm: Convert integer multiply-add 
(indexed) to gvec for aa64 advsimd)
ERROR: space prohibited before that close parenthesis ')'
#105: FILE: target/arm/vec_helper.c:751:
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +,   )

ERROR: space prohibited before that close parenthesis ')'
#109: FILE: target/arm/vec_helper.c:755:
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -,   )

total: 2 errors, 0 warnings, 91 lines checked

Patch 19/20 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

20/20 Checking commit ee9e70cbd125 (target/arm: Convert sq{, r}dmulh to gvec 
for aa64 advsimd)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200815013145.539409-1-richard.henderson@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200815013145.539409-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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