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[RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field
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From: |
frank . chang |
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Subject: |
[RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field |
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Date: |
Mon, 17 Aug 2020 16:48:50 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46c35266cb5..7f937e5b9c8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -494,7 +494,7 @@ static int write_misa(CPURISCVState *env, int csrno,
target_ulong val)
val &= env->misa_mask;
/* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
--
2.17.1
- [RFC v4 00/70] support vector extension v1.0, frank . chang, 2020/08/17
- [RFC v4 01/70] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2020/08/17
- [RFC v4 02/70] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/08/17
- [RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/17
- [RFC v4 04/70] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/17
- [RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field,
frank . chang <=
- [RFC v4 06/70] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/17
- [RFC v4 07/70] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2020/08/17
- [RFC v4 08/70] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/17
- [RFC v4 09/70] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/17
- [RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/08/17
- [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/17
- [RFC v4 11/70] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/17
- [RFC v4 13/70] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/17