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[RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing ve
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From: |
frank . chang |
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Subject: |
[RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers |
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Date: |
Mon, 17 Aug 2020 16:48:55 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6379718e1b6..ed8f6e175f4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,11 @@ static int fs(CPURISCVState *env, int csrno)
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+#endif
return 0;
}
return -1;
--
2.17.1
- [RFC v4 01/70] target/riscv: drop vector 0.7.1 and add 1.0 support, (continued)
- [RFC v4 01/70] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2020/08/17
- [RFC v4 02/70] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/08/17
- [RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/17
- [RFC v4 04/70] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/17
- [RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/08/17
- [RFC v4 06/70] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/17
- [RFC v4 07/70] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2020/08/17
- [RFC v4 08/70] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/17
- [RFC v4 09/70] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/17
- [RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers,
frank . chang <=
- [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/17
- [RFC v4 11/70] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/17
- [RFC v4 13/70] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/17
- [RFC v4 15/70] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/17
- [RFC v4 14/70] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/08/17
- [RFC v4 16/70] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/08/17