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[PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() |
Date: |
Thu, 7 Jan 2021 23:21:54 +0100 |
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
---
target/mips/cpu.h | 5 +++++
target/mips/mips-defs.h | 4 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 0c2d397e4a9..9c45744c5c1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1305,6 +1305,11 @@ static inline bool ase_mt_available(CPUMIPSState *env)
return env->CP0_Config3 & (1 << CP0C3_MT);
}
+static inline bool cpu_type_is_64bit(const char *cpu_type)
+{
+ return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
+}
+
void cpu_set_exception_base(int vp_index, target_ulong address);
/* addr.c */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 1630ae20d59..89a9a4dda31 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -13,7 +13,7 @@
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
-#define ISA_MIPS3 0x0000000000000004ULL
+#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
@@ -71,6 +71,8 @@
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
+#define CPU_MIPS64 (ISA_MIPS3)
+
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
--
2.26.2
- [PULL 00/66] MIPS patches for 2021-01-07, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit(),
Philippe Mathieu-Daudé <=
- [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5, Philippe Mathieu-Daudé, 2021/01/07