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[PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check R
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 |
Date: |
Thu, 7 Jan 2021 23:21:56 +0100 |
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
target/mips/translate.c | 10 +++++-----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 89a9a4dda31..23ce8b8406f 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
@@ -75,7 +74,7 @@
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19933b7868c..172027f9d6e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
switch (reg) {
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -27612,7 +27612,7 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
--
2.26.2
- [PULL 00/66] MIPS patches for 2021-01-07, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1,
Philippe Mathieu-Daudé <=
- [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset(), Philippe Mathieu-Daudé, 2021/01/07