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[PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h'
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' |
Date: |
Thu, 7 Jan 2021 23:22:36 +0100 |
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-18-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index b9cd315c7f4..c61c11978c2 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -164,5 +164,7 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
+void gen_msa(DisasContext *ctx);
+void gen_msa_branch(DisasContext *ctx, uint32_t op1);
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0e7b2abe8bb..e1763e5bcec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28660,7 +28660,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int
wt, int s16, bool if_not)
return true;
}
-static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
+void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -30436,7 +30436,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-static void gen_msa(DisasContext *ctx)
+void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
--
2.26.2
- [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, (continued)
- [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 40/66] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 41/66] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 48/66] target/mips: Extract MSA helper definitions, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h',
Philippe Mathieu-Daudé <=
- [PULL 50/66] target/mips: Extract MSA translation routines, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 54/66] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 59/66] target/mips: Convert Rel6 COP1X opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/07