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[PULL 00/12] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
[PULL 00/12] riscv-to-apply queue |
Date: |
Sun, 17 Jan 2021 13:53:51 -0800 |
The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
Merge remote-tracking branch
'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15
22:21:21 +0000)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
----------------------------------------------------------------
First RISC-V PR for 6.0
This PR:
- Fixes some issues with the m25p80
- Improves GDB support for RISC-V
- Fixes some Linux boot issues, specifiaclly 32-bit boot failures
- Enforces PMP exceptions correctly
- Fixes some Coverity issues
----------------------------------------------------------------
Alistair Francis (1):
riscv: Pass RISCVHartArrayState by pointer
Atish Patra (2):
RISC-V: Place DTB at 3GB boundary instead of 4GB
target/riscv/pmp: Raise exception if no PMP entry is configured
Bin Meng (6):
hw/block: m25p80: Don't write to flash if write is disabled
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
target/riscv: Add CSR name in the CSR function table
target/riscv: Generate the GDB XML file for CSR registers dynamically
target/riscv: Remove built-in GDB XML files for CSRs
Green Wan (1):
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
Sylvain Pelissier (1):
gdb: riscv: Add target description
Xuzhou Cheng (1):
hw/block: m25p80: Implement AAI-WP command support for SST flashes
default-configs/targets/riscv32-linux-user.mak | 2 +-
default-configs/targets/riscv32-softmmu.mak | 2 +-
default-configs/targets/riscv64-linux-user.mak | 2 +-
default-configs/targets/riscv64-softmmu.mak | 2 +-
include/hw/riscv/boot.h | 6 +-
target/riscv/cpu.h | 11 +
target/riscv/pmp.h | 1 +
hw/block/m25p80.c | 74 ++++++
hw/misc/sifive_u_otp.c | 31 ++-
hw/riscv/boot.c | 18 +-
hw/riscv/sifive_u.c | 16 +-
hw/riscv/spike.c | 8 +-
hw/riscv/virt.c | 8 +-
target/riscv/cpu.c | 25 ++
target/riscv/csr.c | 342 ++++++++++++++++++-------
target/riscv/gdbstub.c | 308 ++++------------------
target/riscv/op_helper.c | 5 +
target/riscv/pmp.c | 4 +-
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
20 files changed, 463 insertions(+), 902 deletions(-)
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
- [PULL 00/12] riscv-to-apply queue,
Alistair Francis <=
- [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled, Alistair Francis, 2021/01/17
- [PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes, Alistair Francis, 2021/01/17
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, Alistair Francis, 2021/01/17
- [PULL 03/12] gdb: riscv: Add target description, Alistair Francis, 2021/01/17
- [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type, Alistair Francis, 2021/01/17
- [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured, Alistair Francis, 2021/01/17
- [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB, Alistair Francis, 2021/01/17
- [PULL 09/12] target/riscv: Add CSR name in the CSR function table, Alistair Francis, 2021/01/17
- [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite, Alistair Francis, 2021/01/17
- [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically, Alistair Francis, 2021/01/17