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[PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is config
From: |
Alistair Francis |
Subject: |
[PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured |
Date: |
Sun, 17 Jan 2021 13:53:56 -0800 |
From: Atish Patra <atish.patra@wdc.com>
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.h | 1 +
target/riscv/op_helper.c | 5 +++++
target/riscv/pmp.c | 4 ++--
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 6c6b4c9bef..c8d5ef4a69 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
+uint32_t pmp_get_num_rules(CPURISCVState *env);
#endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d55def76cf..1eddcb94de 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -150,6 +150,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
+
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2eda8e1e2f..80d0334e1b 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t
pmp_index)
/*
* Count the number of active rules.
*/
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
+uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
@@ -237,7 +237,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- return true;
+ return (env->priv == PRV_M) ? true : false;
}
if (size == 0) {
--
2.29.2
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2021/01/17
- [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled, Alistair Francis, 2021/01/17
- [PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes, Alistair Francis, 2021/01/17
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, Alistair Francis, 2021/01/17
- [PULL 03/12] gdb: riscv: Add target description, Alistair Francis, 2021/01/17
- [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type, Alistair Francis, 2021/01/17
- [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured,
Alistair Francis <=
- [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB, Alistair Francis, 2021/01/17
- [PULL 09/12] target/riscv: Add CSR name in the CSR function table, Alistair Francis, 2021/01/17
- [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite, Alistair Francis, 2021/01/17
- [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically, Alistair Francis, 2021/01/17
- [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external, Alistair Francis, 2021/01/17
- [PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs, Alistair Francis, 2021/01/17
- Re: [PULL 00/12] riscv-to-apply queue, Peter Maydell, 2021/01/18