Re: [PATCH 3/3] target/mips: implement Octeon-specific arithmetic instructions

[Richard Henderson]

On 6/7/22 01:59, Pavel Dovgalyuk wrote:
> +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
> +{
> +    TCGv t0, t1;
> +    int p;
> +    TCGLabel *l1;
> +
> +    if (a->rt == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    p = a->p;
> +    if (a->shift) {
> +        p += 32;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    gen_load_gpr(t1, a->rs);
> +
> +    tcg_gen_movi_tl(t0, ((1ULL << (a->lenm1 + 1)) - 1) << p);
> +    tcg_gen_and_tl(t1, t1, t0);
> +    tcg_gen_movi_tl(t0, p);
> +    tcg_gen_shr_tl(cpu_gpr[a->rt], t1, t0);
> +
> +    l1 = gen_new_label();
> +    tcg_gen_movi_tl(t0, 1ULL << a->lenm1);
> +    tcg_gen_and_tl(t0, cpu_gpr[a->rt], t0);
> +    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
> +    tcg_gen_movi_tl(t0, ~((1ULL << (a->lenm1 + 1)) - 1));
> +    tcg_gen_or_tl(cpu_gpr[a->rt], cpu_gpr[a->rt], t0);
> +    gen_set_label(l1);

This is tcg_gen_sextract_tl.

> +static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
> +{
> +    TCGv t0, t1;
> +
> +    if (a->rt == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    gen_load_gpr(t1, a->rs);
> +
> +    tcg_gen_movi_tl(t0, (1ULL << (a->lenm1 + 1)) - 1);
> +    tcg_gen_and_tl(t1, t1, t0);
> +    tcg_gen_movi_tl(t0, a->p + a->shift ? 32 : 0);
> +    tcg_gen_shl_tl(cpu_gpr[a->rt], t1, t0);

This is tcg_gen_deposit_z_tl.

> +static bool trans_POP(DisasContext *ctx, arg_POP *a)
> +{
> +    TCGv t0;
> +
> +    if (a->rd == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    t0 = tcg_temp_new();
> +    gen_load_gpr(t0, a->rs);
> +    if (!a->dw) {
> +        tcg_gen_andi_i64(t0, t0, 0xffffffff);
> +    }
> +    gen_helper_pop(cpu_gpr[a->rd], t0);

This is tcg_gen_ctpop_tl.


r~