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[PATCH v3 0/1] target/riscv: Add Zihintpause support
From: |
Dao Lu |
Subject: |
[PATCH v3 0/1] target/riscv: Add Zihintpause support |
Date: |
Wed, 8 Jun 2022 21:40:44 -0700 |
This patch adds RISC-V Zihintpause support. The extension is set to be enabled
by default and opcode has been added to insn32.decode.
Added trans_pause for TCG to mainly to break reservation and exit the TB.
The change can also be found in:
https://github.com/dlu42/qemu/tree/zihintpause_support_v1
Tested along with pause support added to cpu_relax function for linux, the
changes I made to linux to test can be found here:
https://github.com/dlu42/linux/tree/pause_support_v1
--------
Changelog:
v1 -> v2
1. Pause now also exit the TB and return to main loop
2. Move the REQUIRE_ZIHINTPAUSE macro inside the trans_pause function
v2 -> v3
No changes, v2 was lost from the list
Dao Lu (1):
Add Zihintpause support
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++++++-
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
4 files changed, 27 insertions(+), 1 deletion(-)
--
2.25.1