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[PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shi
From: |
Alistair Francis |
Subject: |
[PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions |
Date: |
Fri, 10 Jun 2022 14:26:45 +1000 |
From: eopXD <yueh.ting.chen@gmail.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 11 +++++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7cdb5d12af..056c2a1c7e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1271,6 +1271,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TS1); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1282,6 +1285,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7)
@@ -1306,6 +1311,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t total_elems = \
+ vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1316,6 +1325,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);\
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 22edf6228d..dbe687fb73 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1831,7 +1831,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a,
GVecGen2sFn32 *gvec_fn,
return false;
}
- if (a->vm && s->vl_eq_vlmax) {
+ if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
TCGv_i32 src1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
@@ -1890,6 +1890,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
--
2.36.1
- [PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working, (continued)
- [PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working, Alistair Francis, 2022/06/10
- [PULL 08/25] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, Alistair Francis, 2022/06/10
- [PULL 11/25] target/riscv: rvv: Early exit when vstart >= vl, Alistair Francis, 2022/06/10
- [PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed, Alistair Francis, 2022/06/10
- [PULL 13/25] target/riscv: rvv: Add tail agnostic for vector load / store instructions, Alistair Francis, 2022/06/10
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, Alistair Francis, 2022/06/10
- [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, Alistair Francis, 2022/06/10
- [PULL 10/25] target/riscv: rvv: Rename ambiguous esz, Alistair Francis, 2022/06/10
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10
- [PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions,
Alistair Francis <=
- [PULL 18/25] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/06/10
- [PULL 19/25] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, Alistair Francis, 2022/06/10
- [PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions, Alistair Francis, 2022/06/10
- [PULL 21/25] target/riscv: rvv: Add tail agnostic for vector mask instructions, Alistair Francis, 2022/06/10
- [PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64, Alistair Francis, 2022/06/10
- [PULL 24/25] target/riscv: Don't expose the CPU properties on names CPUs, Alistair Francis, 2022/06/10
- [PULL 22/25] target/riscv: rvv: Add tail agnostic for vector permutation instructions, Alistair Francis, 2022/06/10
- [PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, Alistair Francis, 2022/06/10
- Re: [PULL 00/25] riscv-to-apply queue, Richard Henderson, 2022/06/10