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[PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction i
From: |
Alistair Francis |
Subject: |
[PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions |
Date: |
Fri, 10 Jun 2022 14:26:50 +1000 |
From: eopXD <yueh.ting.chen@gmail.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-13@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 17390d8d06..174a548ac2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4535,6 +4535,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t vlenb = simd_maxsz(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
@@ -4547,6 +4550,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
} \
*((TD *)vd + HD(0)) = s1; \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, esz, vlenb); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
@@ -4616,6 +4621,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TD); \
+ uint32_t vlenb = simd_maxsz(desc); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
@@ -4628,6 +4636,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
} \
*((TD *)vd + HD(0)) = s1; \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, esz, vlenb); \
}
/* Unordered sum */
@@ -4652,6 +4662,9 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
+ uint32_t esz = sizeof(uint32_t);
+ uint32_t vlenb = simd_maxsz(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t i;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
@@ -4665,6 +4678,8 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
}
*((uint32_t *)vd + H4(0)) = s1;
env->vstart = 0;
+ /* set tail elements to 1s */
+ vext_set_elems_1s(vd, vta, esz, vlenb);
}
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
@@ -4672,6 +4687,9 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
+ uint32_t esz = sizeof(uint64_t);
+ uint32_t vlenb = simd_maxsz(desc);
+ uint32_t vta = vext_vta(desc);
uint32_t i;
uint64_t s1 = *((uint64_t *)vs1);
@@ -4685,6 +4703,8 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
}
*((uint64_t *)vd) = s1;
env->vstart = 0;
+ /* set tail elements to 1s */
+ vext_set_elems_1s(vd, vta, esz, vlenb);
}
/*
--
2.36.1
- [PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed, (continued)
- [PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed, Alistair Francis, 2022/06/10
- [PULL 13/25] target/riscv: rvv: Add tail agnostic for vector load / store instructions, Alistair Francis, 2022/06/10
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, Alistair Francis, 2022/06/10
- [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, Alistair Francis, 2022/06/10
- [PULL 10/25] target/riscv: rvv: Rename ambiguous esz, Alistair Francis, 2022/06/10
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10
- [PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, Alistair Francis, 2022/06/10
- [PULL 18/25] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/06/10
- [PULL 19/25] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, Alistair Francis, 2022/06/10
- [PULL 20/25] target/riscv: rvv: Add tail agnostic for vector reduction instructions,
Alistair Francis <=
- [PULL 21/25] target/riscv: rvv: Add tail agnostic for vector mask instructions, Alistair Francis, 2022/06/10
- [PULL 25/25] target/riscv: trans_rvv: Avoid assert for RV32 and e64, Alistair Francis, 2022/06/10
- [PULL 24/25] target/riscv: Don't expose the CPU properties on names CPUs, Alistair Francis, 2022/06/10
- [PULL 22/25] target/riscv: rvv: Add tail agnostic for vector permutation instructions, Alistair Francis, 2022/06/10
- [PULL 23/25] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, Alistair Francis, 2022/06/10
- Re: [PULL 00/25] riscv-to-apply queue, Richard Henderson, 2022/06/10