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[PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata
From: |
frank . chang |
Subject: |
[PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content |
Date: |
Fri, 10 Jun 2022 13:13:19 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/debug.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index abbcd38a17..089aae0696 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -94,18 +94,23 @@ static inline target_ulong get_trigger_type(CPURISCVState
*env,
return extract_trigger_type(env, tdata1);
}
-static inline target_ulong trigger_type(CPURISCVState *env,
- trigger_type_t type)
+static inline target_ulong build_tdata1(CPURISCVState *env,
+ trigger_type_t type,
+ bool dmode, target_ulong data)
{
target_ulong tdata1;
switch (riscv_cpu_mxl(env)) {
case MXL_RV32:
- tdata1 = RV32_TYPE(type);
+ tdata1 = RV32_TYPE(type) |
+ (dmode ? RV32_DMODE : 0) |
+ (data & RV32_DATA_MASK);
break;
case MXL_RV64:
case MXL_RV128:
- tdata1 = RV64_TYPE(type);
+ tdata1 = RV64_TYPE(type) |
+ (dmode ? RV64_DMODE : 0) |
+ (data & RV64_DATA_MASK);
break;
default:
g_assert_not_reached();
@@ -490,7 +495,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
void riscv_trigger_init(CPURISCVState *env)
{
- target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+ target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
int i;
/* init to type 2 triggers */
--
2.36.1
- [PATCH 0/9] Improve RISC-V Debug support, frank . chang, 2022/06/10
- [PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type, frank . chang, 2022/06/10
- [PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers, frank . chang, 2022/06/10
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content,
frank . chang <=
- [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, frank . chang, 2022/06/10
- [PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written, frank . chang, 2022/06/10
- [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR, frank . chang, 2022/06/10
- [PATCH 6/9] target/riscv: debug: Create common trigger actions function, frank . chang, 2022/06/10
- [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger, frank . chang, 2022/06/10