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[PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger
From: |
frank . chang |
Subject: |
[PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger |
Date: |
Fri, 10 Jun 2022 13:13:24 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/debug.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ab23566113..ce9ff15d75 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -457,6 +457,11 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
pc = env->tdata2[i];
@@ -492,6 +497,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
addr = env->tdata2[i];
flags = 0;
--
2.36.1
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, (continued)
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, frank . chang, 2022/06/10
- [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, frank . chang, 2022/06/10
- [PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written, frank . chang, 2022/06/10
- [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR, frank . chang, 2022/06/10
- [PATCH 6/9] target/riscv: debug: Create common trigger actions function, frank . chang, 2022/06/10
- [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger,
frank . chang <=
- [PATCH 9/9] target/riscv: debug: Add initial support of type 6 trigger, frank . chang, 2022/06/10