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[PULL 20/28] target/arm: Remove default_exception_el
From: |
Peter Maydell |
Subject: |
[PULL 20/28] target/arm: Remove default_exception_el |
Date: |
Fri, 10 Jun 2022 17:07:30 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This function is no longer used. At the same time, remove
DisasContext.secure_routed_to_el3, as it in turn becomes unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.h | 16 ----------------
target/arm/translate-a64.c | 5 -----
target/arm/translate.c | 5 -----
3 files changed, 26 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 850bcdc155e..88dc18a034b 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -43,8 +43,6 @@ typedef struct DisasContext {
int fp_excp_el; /* FP exception EL or 0 if enabled */
int sve_excp_el; /* SVE exception EL or 0 if enabled */
int vl; /* current vector length in bytes */
- /* Flag indicating that exceptions from secure mode are routed to EL3. */
- bool secure_routed_to_el3;
bool vfp_enabled; /* FP enabled via FPSCR.EN */
int vec_len;
int vec_stride;
@@ -199,20 +197,6 @@ static inline int get_mem_index(DisasContext *s)
return arm_to_core_mmu_idx(s->mmu_idx);
}
-/* Function used to determine the target exception EL when otherwise not known
- * or default.
- */
-static inline int default_exception_el(DisasContext *s)
-{
- /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
- * there is no secure EL1, so we route exceptions to EL3. Otherwise,
- * exceptions can only be routed to ELs above 1, so we target the higher of
- * 1 or the current EL.
- */
- return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
- ? 3 : MAX(1, s->current_el);
-}
-
static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
{
/* We don't need to save all of the syndrome so we mask and shift
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4f6181a5483..4c64546090c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14585,11 +14585,6 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->condjmp = 0;
dc->aarch64 = true;
- /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
- * there is no secure EL1, so we route exceptions to EL3.
- */
- dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
- !arm_el_is_aa64(env, 3);
dc->thumb = false;
dc->sctlr_b = 0;
dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 81c27e7c70c..6617de775fd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9319,11 +9319,6 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->condjmp = 0;
dc->aarch64 = false;
- /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
- * there is no secure EL1, so we route exceptions to EL3.
- */
- dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
- !arm_el_is_aa64(env, 3);
dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC);
--
2.25.1
- [PULL 01/28] target/arm: Mark exception helpers as noreturn, (continued)
- [PULL 01/28] target/arm: Mark exception helpers as noreturn, Peter Maydell, 2022/06/10
- [PULL 04/28] target/arm: Move arm_singlestep_active out of line, Peter Maydell, 2022/06/10
- [PULL 05/28] target/arm: Move arm_generate_debug_exceptions out of line, Peter Maydell, 2022/06/10
- [PULL 08/28] target/arm: Move arm_debug_exception_fsr to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 09/28] target/arm: Rename helper_exception_with_syndrome, Peter Maydell, 2022/06/10
- [PULL 12/28] target/arm: Introduce gen_exception_insn, Peter Maydell, 2022/06/10
- [PULL 11/28] target/arm: Rename gen_exception_insn to gen_exception_insn_el, Peter Maydell, 2022/06/10
- [PULL 03/28] target/arm: Move exception_target_el out of line, Peter Maydell, 2022/06/10
- [PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions, Peter Maydell, 2022/06/10
- [PULL 10/28] target/arm: Introduce gen_exception_insn_el_v, Peter Maydell, 2022/06/10
- [PULL 20/28] target/arm: Remove default_exception_el,
Peter Maydell <=
- [PULL 18/28] target/arm: Introduce gen_exception_el_v, Peter Maydell, 2022/06/10
- [PULL 15/28] target/arm: Move gen_exception to translate.c, Peter Maydell, 2022/06/10
- [PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el, Peter Maydell, 2022/06/10
- [PULL 21/28] target/arm: Create raise_exception_debug, Peter Maydell, 2022/06/10
- [PULL 25/28] target/arm: Adjust format test in scr_write, Peter Maydell, 2022/06/10
- [PULL 28/28] semihosting/config: Merge --semihosting-config option groups, Peter Maydell, 2022/06/10
- [PULL 13/28] target/arm: Create helper_exception_swstep, Peter Maydell, 2022/06/10
- [PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL, Peter Maydell, 2022/06/10
- [PULL 16/28] target/arm: Rename gen_exception to gen_exception_el, Peter Maydell, 2022/06/10
- [PULL 19/28] target/arm: Introduce helper_exception_with_syndrome, Peter Maydell, 2022/06/10