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[PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL
From: |
Peter Maydell |
Subject: |
[PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL |
Date: |
Fri, 10 Jun 2022 17:07:24 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We no longer need this value during translation,
as it is now handled within the helpers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 6 ++----
target/arm/translate.h | 2 --
target/arm/helper.c | 12 ++----------
target/arm/translate-a64.c | 1 -
target/arm/translate.c | 1 -
5 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 50b5a9c9fd0..719613ad9ee 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3104,11 +3104,9 @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
/* Target EL if we take a floating-point-disabled exception */
FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
-/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
-FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
-FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1)
+FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
+FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 890e73194c3..8685f55e800 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -59,8 +59,6 @@ typedef struct DisasContext {
*/
uint32_t svc_imm;
int current_el;
- /* Debug target exception level for single-step exceptions */
- int debug_target_el;
GHashTable *cp_regs;
uint64_t features; /* CPU features bits */
bool aarch64;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ac9942d750d..2b2c1998fd1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11102,18 +11102,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState
*env, int fp_el,
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
-static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env)
-{
- CPUARMTBFlags flags = {};
-
- DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
- return flags;
-}
-
static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx)
{
- CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
+ CPUARMTBFlags flags = {};
int el = arm_current_el(env);
if (arm_sctlr(env, el) & SCTLR_A) {
@@ -11139,7 +11131,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState
*env, int fp_el,
static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
ARMMMUIdx mmu_idx)
{
- CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
+ CPUARMTBFlags flags = {};
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
uint64_t sctlr;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 0581118f566..4f6181a5483 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14645,7 +14645,6 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE);
dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS);
dc->is_ldex = false;
- dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
/* Bound the number of insns to execute to those left on the page. */
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c7d422b5415..b8a8972bac9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9350,7 +9350,6 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);
} else {
- dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE);
dc->ns = EX_TBFLAG_A32(tb_flags, NS);
--
2.25.1
- [PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions, (continued)
- [PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions, Peter Maydell, 2022/06/10
- [PULL 10/28] target/arm: Introduce gen_exception_insn_el_v, Peter Maydell, 2022/06/10
- [PULL 20/28] target/arm: Remove default_exception_el, Peter Maydell, 2022/06/10
- [PULL 18/28] target/arm: Introduce gen_exception_el_v, Peter Maydell, 2022/06/10
- [PULL 15/28] target/arm: Move gen_exception to translate.c, Peter Maydell, 2022/06/10
- [PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el, Peter Maydell, 2022/06/10
- [PULL 21/28] target/arm: Create raise_exception_debug, Peter Maydell, 2022/06/10
- [PULL 25/28] target/arm: Adjust format test in scr_write, Peter Maydell, 2022/06/10
- [PULL 28/28] semihosting/config: Merge --semihosting-config option groups, Peter Maydell, 2022/06/10
- [PULL 13/28] target/arm: Create helper_exception_swstep, Peter Maydell, 2022/06/10
- [PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL,
Peter Maydell <=
- [PULL 16/28] target/arm: Rename gen_exception to gen_exception_el, Peter Maydell, 2022/06/10
- [PULL 19/28] target/arm: Introduce helper_exception_with_syndrome, Peter Maydell, 2022/06/10
- [PULL 07/28] target/arm: Move exception_bkpt_insn to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 17/28] target/arm: Introduce gen_exception, Peter Maydell, 2022/06/10
- [PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12], Peter Maydell, 2022/06/10
- [PULL 22/28] target/arm: Move arm_debug_target_el to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 24/28] tests/qtest: Reduce npcm7xx_sdhci test image size, Peter Maydell, 2022/06/10
- [PULL 27/28] gdbstub: Don't use GDB syscalls if no GDB is attached, Peter Maydell, 2022/06/10
- Re: [PULL 00/28] target-arm queue, Richard Henderson, 2022/06/10