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[PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
From: |
Peter Maydell |
Subject: |
[PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] |
Date: |
Fri, 10 Jun 2022 17:07:36 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Since DDI0487F.a, the RW bit is RAO/WI. When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/helper.c | 4 ++++
2 files changed, 9 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 161ac9fa2ee..df677b2d5d2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3854,6 +3854,11 @@ static inline bool isar_feature_aa64_aa32_el1(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
}
+static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
+}
+
static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ff9f9fe6ee4..6457e6301cd 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1747,6 +1747,10 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
value |= SCR_FW | SCR_AW; /* RES1 */
valid_mask &= ~SCR_NET; /* RES0 */
+ if (!cpu_isar_feature(aa64_aa32_el1, cpu) &&
+ !cpu_isar_feature(aa64_aa32_el2, cpu)) {
+ value |= SCR_RW; /* RAO/WI */
+ }
if (cpu_isar_feature(aa64_ras, cpu)) {
valid_mask |= SCR_TERR;
}
--
2.25.1
- [PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el, (continued)
- [PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el, Peter Maydell, 2022/06/10
- [PULL 21/28] target/arm: Create raise_exception_debug, Peter Maydell, 2022/06/10
- [PULL 25/28] target/arm: Adjust format test in scr_write, Peter Maydell, 2022/06/10
- [PULL 28/28] semihosting/config: Merge --semihosting-config option groups, Peter Maydell, 2022/06/10
- [PULL 13/28] target/arm: Create helper_exception_swstep, Peter Maydell, 2022/06/10
- [PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL, Peter Maydell, 2022/06/10
- [PULL 16/28] target/arm: Rename gen_exception to gen_exception_el, Peter Maydell, 2022/06/10
- [PULL 19/28] target/arm: Introduce helper_exception_with_syndrome, Peter Maydell, 2022/06/10
- [PULL 07/28] target/arm: Move exception_bkpt_insn to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 17/28] target/arm: Introduce gen_exception, Peter Maydell, 2022/06/10
- [PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12],
Peter Maydell <=
- [PULL 22/28] target/arm: Move arm_debug_target_el to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 24/28] tests/qtest: Reduce npcm7xx_sdhci test image size, Peter Maydell, 2022/06/10
- [PULL 27/28] gdbstub: Don't use GDB syscalls if no GDB is attached, Peter Maydell, 2022/06/10
- Re: [PULL 00/28] target-arm queue, Richard Henderson, 2022/06/10