[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigge
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger |
|
Date: |
Wed, 15 Jun 2022 20:43:54 +0800 |
On Fri, Jun 10, 2022 at 1:25 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Type 2 trigger cannot be fired in VU/VS modes.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/debug.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, (continued)
- [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, frank . chang, 2022/06/10
- [PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written, frank . chang, 2022/06/10
- [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR, frank . chang, 2022/06/10
- [PATCH 6/9] target/riscv: debug: Create common trigger actions function, frank . chang, 2022/06/10
- [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger, frank . chang, 2022/06/10
- Re: [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger,
Bin Meng <=
- [PATCH 9/9] target/riscv: debug: Add initial support of type 6 trigger, frank . chang, 2022/06/10