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[PULL 1/9] tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]
From: |
Richard Henderson |
Subject: |
[PULL 1/9] tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd] |
Date: |
Tue, 21 Jun 2022 13:46:35 -0700 |
From: Matheus Kowalczuk Ferst <matheus.ferst@eldorado.org.br>
Power ISA v3.0 introduced mod[su][wd] insns that can be used to
implement rem[u]_i{32,64}.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.h | 4 ++--
tcg/ppc/tcg-target.c.inc | 22 ++++++++++++++++++++++
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index e6cf72503f..b5cd225cfa 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -83,7 +83,7 @@ extern bool have_vsx;
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
-#define TCG_TARGET_HAS_rem_i32 0
+#define TCG_TARGET_HAS_rem_i32 have_isa_3_00
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
@@ -117,7 +117,7 @@ extern bool have_vsx;
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div_i64 1
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_rem_i64 have_isa_3_00
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index de4483e43b..1cbd047ab3 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -371,6 +371,8 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define MULHWU XO31( 11)
#define DIVW XO31(491)
#define DIVWU XO31(459)
+#define MODSW XO31(779)
+#define MODUW XO31(267)
#define CMP XO31( 0)
#define CMPL XO31( 32)
#define LHBRX XO31(790)
@@ -403,6 +405,8 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define MULHDU XO31( 9)
#define DIVD XO31(489)
#define DIVDU XO31(457)
+#define MODSD XO31(777)
+#define MODUD XO31(265)
#define LBZX XO31( 87)
#define LHZX XO31(279)
@@ -2806,6 +2810,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
break;
+ case INDEX_op_rem_i32:
+ tcg_out32(s, MODSW | TAB(args[0], args[1], args[2]));
+ break;
+
+ case INDEX_op_remu_i32:
+ tcg_out32(s, MODUW | TAB(args[0], args[1], args[2]));
+ break;
+
case INDEX_op_shl_i32:
if (const_args[2]) {
/* Limit immediate shift count lest we create an illegal insn. */
@@ -2947,6 +2959,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_divu_i64:
tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
break;
+ case INDEX_op_rem_i64:
+ tcg_out32(s, MODSD | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_remu_i64:
+ tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
+ break;
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args, false);
@@ -3722,6 +3740,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
+ case INDEX_op_rem_i32:
+ case INDEX_op_remu_i32:
case INDEX_op_nand_i32:
case INDEX_op_nor_i32:
case INDEX_op_muluh_i32:
@@ -3732,6 +3752,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_nor_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i64:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
return C_O1_I2(r, r, r);
--
2.34.1
- [PULL 0/9] tcg patch queue for 2022-06-21, Richard Henderson, 2022/06/21
- [PULL 6/9] softmmu: Always initialize xlat in address_space_translate_for_iotlb, Richard Henderson, 2022/06/21
- [PULL 4/9] accel/tcg: Reorganize tcg_accel_ops_init(), Richard Henderson, 2022/06/21
- [PULL 8/9] util/cacheflush: Merge aarch64 ctr_el0 usage, Richard Henderson, 2022/06/21
- [PULL 5/9] qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all, Richard Henderson, 2022/06/21
- [PULL 2/9] target/avr: Drop avr_cpu_memory_rw_debug(), Richard Henderson, 2022/06/21
- [PULL 1/9] tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd],
Richard Henderson <=
- [PULL 7/9] util: Merge cacheflush.c and cacheinfo.c, Richard Henderson, 2022/06/21
- [PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent icache, Richard Henderson, 2022/06/21
- [PULL 3/9] accel/tcg: Init TCG cflags in vCPU thread handler, Richard Henderson, 2022/06/21
- Re: [PULL 0/9] tcg patch queue for 2022-06-21, Richard Henderson, 2022/06/21