[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent
From: |
Richard Henderson |
Subject: |
[PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent icache |
Date: |
Tue, 21 Jun 2022 13:46:43 -0700 |
From: Nicholas Piggin <npiggin@gmail.com>
On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates
that we can use a simplified 3 instruction flush sequence.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220519141131.29839-1-npiggin@gmail.com>
[rth: update after merging cacheflush.c and cacheinfo.c]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org>
---
util/cacheflush.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/util/cacheflush.c b/util/cacheflush.c
index 01b6cb7583..2c2c73e085 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -117,6 +117,10 @@ static void sys_cache_info(int *isize, int *dsize)
* Architecture (+ OS) specific cache detection mechanisms.
*/
+#if defined(__powerpc__)
+static bool have_coherent_icache;
+#endif
+
#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
/* Apple does not expose CTR_EL0, so we must use system interfaces. */
static uint64_t save_ctr_el0;
@@ -156,6 +160,7 @@ static void arch_cache_info(int *isize, int *dsize)
if (*dsize == 0) {
*dsize = qemu_getauxval(AT_DCACHEBSIZE);
}
+ have_coherent_icache = qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE_SNOOP;
}
#else
@@ -298,8 +303,24 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw,
size_t len)
void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
{
uintptr_t p, b, e;
- size_t dsize = qemu_dcache_linesize;
- size_t isize = qemu_icache_linesize;
+ size_t dsize, isize;
+
+ /*
+ * Some processors have coherent caches and support a simplified
+ * flushing procedure. See
+ * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)
+ * https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
+ */
+ if (have_coherent_icache) {
+ asm volatile ("sync\n\t"
+ "icbi 0,%0\n\t"
+ "isync"
+ : : "r"(rx) : "memory");
+ return;
+ }
+
+ dsize = qemu_dcache_linesize;
+ isize = qemu_icache_linesize;
b = rw & ~(dsize - 1);
e = (rw + len + dsize - 1) & ~(dsize - 1);
--
2.34.1
- [PULL 0/9] tcg patch queue for 2022-06-21, Richard Henderson, 2022/06/21
- [PULL 6/9] softmmu: Always initialize xlat in address_space_translate_for_iotlb, Richard Henderson, 2022/06/21
- [PULL 4/9] accel/tcg: Reorganize tcg_accel_ops_init(), Richard Henderson, 2022/06/21
- [PULL 8/9] util/cacheflush: Merge aarch64 ctr_el0 usage, Richard Henderson, 2022/06/21
- [PULL 5/9] qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all, Richard Henderson, 2022/06/21
- [PULL 2/9] target/avr: Drop avr_cpu_memory_rw_debug(), Richard Henderson, 2022/06/21
- [PULL 1/9] tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd], Richard Henderson, 2022/06/21
- [PULL 7/9] util: Merge cacheflush.c and cacheinfo.c, Richard Henderson, 2022/06/21
- [PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent icache,
Richard Henderson <=
- [PULL 3/9] accel/tcg: Init TCG cflags in vCPU thread handler, Richard Henderson, 2022/06/21
- Re: [PULL 0/9] tcg patch queue for 2022-06-21, Richard Henderson, 2022/06/21