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Re: [PATCH v3 34/51] target/arm: Implement PSEL
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 34/51] target/arm: Implement PSEL |
Date: |
Fri, 24 Jun 2022 13:51:44 +0100 |
On Mon, 20 Jun 2022 at 19:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Would be helpful to note in the commit message that this is an
SVE instruction that operates using the SVE vector length but that
it is present only if SME is implemented.
> +static bool trans_PSEL(DisasContext *s, arg_psel *a)
> +{
> + int vl = vec_full_reg_size(s);
> + int pl = pred_gvec_reg_size(s);
> + int elements = vl >> a->esz;
> + TCGv_i64 tmp, didx, dbit;
> + TCGv_ptr ptr;
> +
> + if (!dc_isar_feature(aa64_sme, s)) {
> + return false;
> + }
> + if (!sve_access_check(s)) {
> + return true;
> + }
> +
> + tmp = tcg_temp_new_i64();
> + dbit = tcg_temp_new_i64();
> + didx = tcg_temp_new_i64();
> + ptr = tcg_temp_new_ptr();
> +
> + /* Compute the predicate element. */
> + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm);
> + if (is_power_of_2(elements)) {
> + tcg_gen_andi_i64(tmp, tmp, elements - 1);
> + } else {
> + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements));
> + }
> +
> + /* Extract the predicate byte and bit indices. */
> + tcg_gen_shli_i64(tmp, tmp, a->esz);
> + tcg_gen_andi_i64(dbit, tmp, 7);
> + tcg_gen_shri_i64(didx, tmp, 3);
> + if (HOST_BIG_ENDIAN) {
> + tcg_gen_xori_i64(didx, didx, 7);
> + }
> +
> + /* Load the predicate word. */
> + tcg_gen_trunc_i64_ptr(ptr, didx);
> + tcg_gen_add_ptr(ptr, ptr, cpu_env);
> + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
> +
> + /* Extract the predicate bit and replicate to MO_64. */
> + tcg_gen_shr_i64(tmp, tmp, dbit);
> + tcg_gen_andi_i64(tmp, tmp, 1);
> + tcg_gen_neg_i64(tmp, tmp);
> +
> + /* Apply to either copy the source, or write zeros. */
> + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd),
> + pred_full_reg_offset(s, a->pn), tmp, pl, pl);
> +
> + tcg_temp_free_i64(tmp);
> + tcg_temp_free_i64(dbit);
> + tcg_temp_free_i64(didx);
> + tcg_temp_free_ptr(ptr);
> + return true;
> +}
Suspect this would be clearer to read as a helper function, but
it's not that long as a series of TCG ops, I suppose.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v3 27/51] target/arm: Export unpredicated ld/st from translate-sve.c, (continued)
- [PATCH v3 29/51] target/arm: Implement SME ADDHA, ADDVA, Richard Henderson, 2022/06/20
- [PATCH v3 32/51] target/arm: Implement FMOPA, FMOPS (widening), Richard Henderson, 2022/06/20
- [PATCH v3 34/51] target/arm: Implement PSEL, Richard Henderson, 2022/06/20
- Re: [PATCH v3 34/51] target/arm: Implement PSEL,
Peter Maydell <=
- [PATCH v3 35/51] target/arm: Implement REVD, Richard Henderson, 2022/06/20
- [PATCH v3 38/51] target/arm: Enable SME for -cpu max, Richard Henderson, 2022/06/20
- [PATCH v3 30/51] target/arm: Implement FMOPA, FMOPS (non-widening), Richard Henderson, 2022/06/20
- [PATCH v3 37/51] target/arm: Reset streaming sve state on exception boundaries, Richard Henderson, 2022/06/20
- [PATCH v3 33/51] target/arm: Implement SME integer outer product, Richard Henderson, 2022/06/20