Re: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Jiaxun Yang]

> 2022年12月10日 15:55，Philippe Mathieu-Daudé <philmd@linaro.org> 写道：
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/mips/bootloader.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index cc3df385df..541b59bf84 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -177,9 +177,32 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, 
> uint16_t imm)
>     }
> }
> 
> +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t offset)
> +{
> +    uint16_t *p = (uint16_t *)*ptr;
> +    uint32_t insn = 0;
> +
> +    insn = deposit32(insn, 26, 6, 0b100001);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 16, 5, rs);
> +    insn = deposit32(insn, 12, 4, 0b1001);
> +    insn = deposit32(insn, 0, 12, offset);
> +
> +    stw_p(p, insn >> 16);
> +    p++;
> +    stw_p(p, insn >> 0);
> +    p++;

Think we can have a helper function like st_nm32_p.

Thanks
- Jiaxun

> +
> +    *ptr = p;
> +}
> +
> static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> {
> -    bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        bl_gen_sw_nm(p, rt, base, offset);
> +    } else {
> +        bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    }
> }
> 
> static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> -- 
> 2.38.1
>