---------------------------------
From b1789f2523d06798b8883664bfa9a9df797bfccf Mon Sep 17 00:00:00 2001
From: Wenchao Wang <wenchao.wang@intel.com <mailto:wenchao.wang@intel.com>>
Date: Fri, 25 Nov 2022 18:37:34 +0800
Subject: [PATCH] target/i386/hax: Add XCR0 support
Introduce extended control register XCR0 to support XSAVE feature set.
Note: This change requires at least HAXM v7.8.0 to support.
Reviewed-by: Hang Yuan <hang.yuan@intel.com <mailto:hang.yuan@intel.com>>
Signed-off-by: Wenchao Wang <wenchao.wang@intel.com
<mailto:wenchao.wang@intel.com>>
---
target/i386/hax/hax-interface.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/hax/hax-interface.h
b/target/i386/hax/hax-interface.h index 537ae084e9..1d13bb2380 100644
--- a/target/i386/hax/hax-interface.h
+++ b/target/i386/hax/hax-interface.h
@@ -201,6 +201,8 @@ struct vcpu_state_t {
uint64_t _cr3;
uint64_t _cr4;
+ uint64_t _xcr0;
+
uint64_t _dr0;
uint64_t _dr1;
uint64_t _dr2;
--
2.17.1