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[PATCH v2 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev prope
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property |
Date: |
Tue, 20 Dec 2022 12:34:33 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This device does not have to be TARGET-dependent.
Add a 'cpu_big_endian' property which sets the byte-swapping
options if required.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221209151533.69516-5-philmd@linaro.org>
---
hw/mips/gt64xxx_pci.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f6fa309ef7..4cafc76a23 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
+#include "hw/qdev-properties.h"
#include "hw/registerfields.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
@@ -256,6 +257,9 @@ struct GT64120State {
PCI_MAPPING_ENTRY(ISD);
MemoryRegion pci0_mem;
AddressSpace pci0_mem_as;
+
+ /* properties */
+ bool cpu_little_endian;
};
/* Adjust range to avoid touching space which isn't mappable via PCI */
@@ -998,16 +1002,11 @@ static const MemoryRegionOps isd_mem_ops = {
static void gt64120_reset(DeviceState *dev)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
-#if TARGET_BIG_ENDIAN
- bool cpu_little_endian = false;
-#else
- bool cpu_little_endian = true;
-#endif
/* FIXME: Malta specific hw assumptions ahead */
/* CPU Configuration */
- s->regs[GT_CPU] = cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
+ s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
s->regs[GT_MULTI] = 0x00000003;
/* CPU Address decode */
@@ -1114,7 +1113,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_TC_CONTROL] = 0x00000000;
/* PCI Internal */
- s->regs[GT_PCI0_CMD] = cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
+ s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK
: 0;
s->regs[GT_PCI0_TOR] = 0x0000070f;
s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
@@ -1131,7 +1130,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
- s->regs[GT_PCI1_CMD] = cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
+ s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK
: 0;
s->regs[GT_PCI1_TOR] = 0x0000070f;
s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
@@ -1224,11 +1223,18 @@ static const TypeInfo gt64120_pci_info = {
},
};
+static Property gt64120_properties[] = {
+ DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
+ cpu_little_endian, !TARGET_BIG_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void gt64120_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ device_class_set_props(dc, gt64120_properties);
dc->realize = gt64120_realize;
dc->reset = gt64120_reset;
dc->vmsd = &vmstate_gt64120;
--
2.38.1
- [PATCH v2 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 1/7] hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 2/7] hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 3/7] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields API, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property,
Philippe Mathieu-Daudé <=
- [PATCH v2 5/7] hw/mips/malta: Explicit GT64120 endianness upon device creation, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 6/7] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2022/12/20
- [PATCH v2 7/7] hw/mips/gt64xxx_pci: Move it to hw/pci-host/, Philippe Mathieu-Daudé, 2022/12/20
- Re: [PATCH v2 0/7] hw/mips: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2022/12/21