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[PULL 33/41] hw/cxl/device: Add Flex Bus Port DVSEC
From: |
Michael S. Tsirkin |
Subject: |
[PULL 33/41] hw/cxl/device: Add Flex Bus Port DVSEC |
Date: |
Wed, 21 Dec 2022 08:06:16 -0500 |
From: Ira Weiny <ira.weiny@intel.com>
The Flex Bus Port DVSEC was missing on type 3 devices which was blocking
RAS checks.[1]
Add the Flex Bus Port DVSEC to type 3 devices as per CXL 3.0 8.2.1.3.
[1]
https://lore.kernel.org/linux-cxl/167096738875.2861540.11815053323626849940.stgit@djiang5-desk3.ch.intel.com/
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>
Cc: qemu-devel@nongnu.org
Cc: linux-cxl@vger.kernel.org
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Message-Id: <20221213-ira-flexbus-port-v2-1-eaa48d0e0700@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/mem/cxl_type3.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 255590201a..dae4fd89ca 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -295,6 +295,17 @@ static void build_dvsecs(CXLType3Dev *ct3d)
cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
GPF_DEVICE_DVSEC_LENGTH, GPF_DEVICE_DVSEC,
GPF_DEVICE_DVSEC_REVID, dvsec);
+
+ dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
+ .cap = 0x26, /* 68B, IO, Mem, non-MLD */
+ .ctrl = 0x02, /* IO always enabled */
+ .status = 0x26, /* same as capabilities */
+ .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
+ };
+ cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
+ PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
+ PCIE_FLEXBUS_PORT_DVSEC,
+ PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
}
static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
--
MST
- [PULL 21/41] vdpa: store x-svq parameter in VhostVDPAState, (continued)
- [PULL 21/41] vdpa: store x-svq parameter in VhostVDPAState, Michael S. Tsirkin, 2022/12/21
- [PULL 22/41] vdpa: add shadow_data to vhost_vdpa, Michael S. Tsirkin, 2022/12/21
- [PULL 25/41] include/hw: attempt to document VirtIO feature variables, Michael S. Tsirkin, 2022/12/21
- [PULL 23/41] vdpa: always start CVQ in SVQ mode if possible, Michael S. Tsirkin, 2022/12/21
- [PULL 19/41] vdpa: allocate SVQ array unconditionally, Michael S. Tsirkin, 2022/12/21
- [PULL 27/41] vhost: fix vq dirty bitmap syncing when vIOMMU is enabled, Michael S. Tsirkin, 2022/12/21
- [PULL 29/41] pci: drop redundant PCIDeviceClass::is_bridge field, Michael S. Tsirkin, 2022/12/21
- [PULL 30/41] docs/acpi/bits: document BITS_DEBUG environment variable, Michael S. Tsirkin, 2022/12/21
- [PULL 34/41] hw/virtio: Add missing "hw/core/cpu.h" include, Michael S. Tsirkin, 2022/12/21
- [PULL 28/41] remove DEC 21154 PCI bridge, Michael S. Tsirkin, 2022/12/21
- [PULL 33/41] hw/cxl/device: Add Flex Bus Port DVSEC,
Michael S. Tsirkin <=
- [PULL 31/41] acpi/tests/avocado/bits: add mformat as one of the dependencies, Michael S. Tsirkin, 2022/12/21
- [PULL 32/41] hw/acpi: Rename tco.c -> ich9_tco.c, Michael S. Tsirkin, 2022/12/21
- [PULL 35/41] hw/virtio: Rename virtio_ss[] -> specific_virtio_ss[], Michael S. Tsirkin, 2022/12/21
- [PULL 38/41] hw/virtio: Extract config read/write accessors to virtio-config-io.c, Michael S. Tsirkin, 2022/12/21
- [PULL 40/41] libvhost-user: Switch to unsigned int for inuse field in struct VuVirtq, Michael S. Tsirkin, 2022/12/21
- [PULL 41/41] contrib/vhost-user-blk: Replace lseek64 with lseek, Michael S. Tsirkin, 2022/12/21
- [PULL 36/41] hw/virtio: Guard and restrict scope of qmp_virtio_feature_map_t[], Michael S. Tsirkin, 2022/12/21
- [PULL 37/41] hw/virtio: Constify qmp_virtio_feature_map_t[], Michael S. Tsirkin, 2022/12/21
- [PULL 39/41] hw/virtio: Extract QMP related code virtio-qmp.c, Michael S. Tsirkin, 2022/12/21
- Re: [PULL 00/41] virtio,pc,pci: features, cleanups, fixes, Peter Maydell, 2022/12/21