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[PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro
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From: |
Alistair Francis |
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Subject: |
[PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro |
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Date: |
Thu, 22 Dec 2022 08:39:39 +1000 |
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Adds a helper macro that implements the register `w1c`
functionality.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.
If the field is cleared (0), then no change and
val is returned.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221017054950.317584-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/registerfields.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 1330ca77de..0b8404c2f7 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -115,6 +115,28 @@
R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
_d; })
+/*
+ * Clear the specified field in storage if
+ * any field bits are set, else no changes made. Implements
+ * single/multi-bit `w1c`
+ *
+ */
+#define FIELD8_1CLEAR(storage, reg, field) \
+ (FIELD_EX8(storage, reg, field) ? \
+ FIELD_DP8(storage, reg, field, 0x00) : storage)
+
+#define FIELD16_1CLEAR(storage, reg, field) \
+ (FIELD_EX16(storage, reg, field) ? \
+ FIELD_DP16(storage, reg, field, 0x00) : storage)
+
+#define FIELD32_1CLEAR(storage, reg, field) \
+ (FIELD_EX32(storage, reg, field) ? \
+ FIELD_DP32(storage, reg, field, 0x00) : storage)
+
+#define FIELD64_1CLEAR(storage, reg, field) \
+ (FIELD_EX64(storage, reg, field) ? \
+ FIELD_DP64(storage, reg, field, 0x00) : storage)
+
#define FIELD_SDP8(storage, reg, field, val) ({ \
struct { \
signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
--
2.38.1
- [PULL v2 00/45] riscv-to-apply queue, Alistair Francis, 2022/12/21
- [PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro,
Alistair Francis <=
- [PULL v2 01/45] target/riscv: Fix PMP propagation for tlb, Alistair Francis, 2022/12/21
- [PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2, Alistair Francis, 2022/12/21
- [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro, Alistair Francis, 2022/12/21
- [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12, Alistair Francis, 2022/12/21
- [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2022/12/21
- [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2022/12/21
- [PULL v2 07/45] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2022/12/21
- [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/21
- [PULL v2 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/21
- [PULL v2 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/21