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[PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
From: |
Alistair Francis |
Subject: |
[PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC |
Date: |
Thu, 22 Dec 2022 08:40:07 +1000 |
From: Bin Meng <bmeng@tinylab.org>
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().
Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/Kconfig | 1 +
hw/riscv/Kconfig | 5 -----
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index ecd2883ceb..1d4573e803 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -78,6 +78,7 @@ config RISCV_IMSIC
config SIFIVE_PLIC
bool
+ select MSI_NONBROKEN
config GOLDFISH_PIC
bool
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 79ff61c464..167dc4cca6 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -11,7 +11,6 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
select MCHP_PFSOC_SYSREG
- select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_PDMA
select SIFIVE_PLIC
@@ -37,7 +36,6 @@ config RISCV_VIRT
imply TPM_TIS_SYSBUS
select RISCV_NUMA
select GOLDFISH_RTC
- select MSI_NONBROKEN
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
@@ -53,7 +51,6 @@ config RISCV_VIRT
config SIFIVE_E
bool
- select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
@@ -64,7 +61,6 @@ config SIFIVE_E
config SIFIVE_U
bool
select CADENCE
- select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
@@ -82,6 +78,5 @@ config SPIKE
bool
select RISCV_NUMA
select HTIF
- select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_PLIC
--
2.38.1
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, (continued)
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/21
- [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/21
- [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/21
- [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/21
- [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured, Alistair Francis, 2022/12/21
- [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2022/12/21
- [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/21
- [PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2022/12/21
- [PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC,
Alistair Francis <=
- [PULL v2 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/21
- [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/21
- [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/21
- [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/21
- [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2022/12/21
- [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Alistair Francis, 2022/12/21
- [PULL v2 34/45] hw/riscv: spike: Remove misleading comments, Alistair Francis, 2022/12/21
- [PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Alistair Francis, 2022/12/21
- [PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value, Alistair Francis, 2022/12/21
- [PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Alistair Francis, 2022/12/21