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[PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule
From: |
Alistair Francis |
Subject: |
[PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured |
Date: |
Thu, 22 Dec 2022 08:40:02 +1000 |
From: Bin Meng <bmeng@tinylab.org>
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault exception.
At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.
Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is
configured")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221205065303.204095-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 09f1f5185d..d7af7f056b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
--
2.38.1
- [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, (continued)
- [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/21
- [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/21
- [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/21
- [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/21
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/21
- [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/21
- [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/21
- [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/21
- [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured,
Alistair Francis <=
- [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2022/12/21
- [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/21
- [PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2022/12/21
- [PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/21
- [PULL v2 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/21
- [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/21
- [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/21
- [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/21
- [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2022/12/21
- [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Alistair Francis, 2022/12/21