Re: [PATCH 6/9] hw/arm/aspeed_ast10x0: Map HACE peripheral

[Peter Delevoryas]

On Thu, Dec 29, 2022 at 04:23:22PM +0100, Philippe Mathieu-Daudé wrote:
> Since I don't have access to the datasheet, the relevant
> values were found in:
> https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
> 
> Before on Zephyr:
> 
>   uart:~$ crypto aes256_cbc_vault
>   aes256_cbc vault key 1
>   [00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup
>   [00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098
>   [00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340
>   [00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348
>   [00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300
>   [00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040
>   [00:00:06.699,000] <inf> hace_global: crypto_cmd_reg:  11c2098
>   [00:00:09.743,000] <inf> hace_global: HACE_STS: 0
>   [00:00:09.743,000] <err> hace_global: HACE poll timeout
>   [00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed
>   [00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free
>   uart:~$
> 
> After:
> 
>   uart:~$ crypto aes256_cbc_vault
>   aes256_cbc vault key 1
>   Was waiting for:
>   6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
>   ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
>   30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
>   f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
> 
>    But got:
>   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
>   [00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup
>   [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098
>   [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
>   [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
>   [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
>   [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
>   [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2098
>   [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
>   [00:00:05.772,000] <inf> crypto: Output length (encryption): 80
>   [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free
>   [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup
>   [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018
>   [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
>   [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
>   [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
>   [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
>   [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2018
>   [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
>   [00:00:05.772,000] <inf> crypto: Output length (decryption): 64
>   [00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between 
> plaintext and decrypted cipher text
>   [00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free
>   uart:~$
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Awesome!

Reviewed-by: Peter Delevoryas <peter@pjd.dev>

> ---
> Should we rename HACE 'dram' as 'secram' / 'secure-ram'?

Sure, sounds good to me.

> ---
>  hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 21a2e62345..02636705b6 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -29,6 +29,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
>      [ASPEED_DEV_SPI1]      = 0x7E630000,
>      [ASPEED_DEV_SPI2]      = 0x7E640000,
>      [ASPEED_DEV_UDC]       = 0x7E6A2000,
> +    [ASPEED_DEV_HACE]      = 0x7E6D0000,
>      [ASPEED_DEV_SCU]       = 0x7E6E2000,
>      [ASPEED_DEV_JTAG0]     = 0x7E6E4000,
>      [ASPEED_DEV_JTAG1]     = 0x7E6E4100,
> @@ -166,6 +167,9 @@ static void aspeed_soc_ast1030_init(Object *obj)
>      snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
>      object_initialize_child(obj, "gpio", &s->gpio, typename);
>  
> +    snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
> +    object_initialize_child(obj, "hace", &s->hace, typename);
> +
>      object_initialize_child(obj, "iomem", &s->iomem, 
> TYPE_UNIMPLEMENTED_DEVICE);
>      object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
>                              TYPE_UNIMPLEMENTED_DEVICE);
> @@ -359,6 +363,17 @@ static void aspeed_soc_ast1030_realize(DeviceState 
> *dev_soc, Error **errp)
>      }
>      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, 
> sc->memmap[ASPEED_DEV_SBC]);
>  
> +    /* HACE */
> +    object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->secsram),
> +                             &error_abort);
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
> +        return;
> +    }
> +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
> +                    sc->memmap[ASPEED_DEV_HACE]);
> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
> +                       aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
> +
>      /* Watch dog */
>      for (i = 0; i < sc->wdts_num; i++) {
>          AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> -- 
> 2.38.1
>