Re: [PATCH v3 2/2] target/riscv: Add RVV registers to log

[Philippe Mathieu-Daudé]

On 2/6/23 05:43, Alistair Francis wrote:
> On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
> > Print RvV extesion register to log if VPU option is enabled.
> >
> > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
>
> I applied the first patch, unfortunately this one doesn't apply
> anymore. Do you mind rebasing this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next
>
> Alistair
>
> > ---
> >   target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 55 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 5bc0005cc7..cfd063a5dc 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] = {
> >     "f30/ft10", "f31/ft11"
> >   };
> >
> > +const char * const riscv_rvv_regnames[] = {
> > +  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
> > +  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
> > +  "v14", "v15", "v16", "v17", "v18", "v19", "v20",
> > +  "v21", "v22", "v23", "v24", "v25", "v26", "v27",
> > +  "v28", "v29", "v30", "v31"
> > +};
> > +
> >   static const char * const riscv_excp_names[] = {
> >       "misaligned_fetch",
> >       "fault_fetch",
> > @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int 
> > flags)
> >   {
> >       RISCVCPU *cpu = RISCV_CPU(cs);
> >       CPURISCVState *env = &cpu->env;
> > -    int i;
> > +    int i, j;
> > +    uint8_t *p;
> >
> >   #if !defined(CONFIG_USER_ONLY)
> >       if (riscv_has_ext(env, RVH)) {
> > @@ -506,6 +515,51 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, 
> > int flags)
> >               }
> >           }
> >       }
> > +    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> > +        static const int dump_rvv_csrs[] = {
> > +                    CSR_VSTART,
> > +                    CSR_VXSAT,
> > +                    CSR_VXRM,
> > +                    CSR_VCSR,
> > +                    CSR_VL,
> > +                    CSR_VTYPE,
> > +                    CSR_VLENB,
> > +                };
> > +        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> > +            int csrno = dump_rvv_csrs[i];
> > +            target_ulong val = 0;
> > +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> > +
> > +            /*
> > +             * Rely on the smode, hmode, etc, predicates within csr.c
> > +             * to do the filtering of the registers that are present.
> > +             */
> > +            if (res == RISCV_EXCP_NONE) {
> > +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> > +                             csr_ops[csrno].name, val);
> > +            }
> > +        }
> > +        uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> > +
> > +/*
> > + * From vector_helper.c
> > + * Note that vector data is stored in host-endian 64-bit chunks,
> > + * so addressing bytes needs a host-endian fixup.

Hmm we should have a ld/st API helper for that. Maybe something like:

  uint64_t val = ldq_he_p(env->vreg[i * vlenb]);

> > + */
> > +#if HOST_BIG_ENDIAN
> > +#define BYTE(x)   ((x) ^ 7)
> > +#else
> > +#define BYTE(x)   (x)
> > +#endif
> > +        for (i = 0; i < 32; i++) {
> > +            qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> > +            p = (uint8_t *)env->vreg;
> > +            for (j = vlenb - 1 ; j >= 0; j--) {
> > +                qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
> > +            }
> > +            qemu_fprintf(f, "\n");
> > +        }
> > +    }
> >   }
> >
> >   static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> > --
> > 2.34.1