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[PULL v2 06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception numbe
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From: |
Alistair Francis |
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Subject: |
[PULL v2 06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 |
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Date: |
Mon, 3 Jun 2024 21:16:22 +1000 |
From: Clément Léger <cleger@rivosinc.com>
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fc2068ee4d..74318a925c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -670,11 +670,11 @@ typedef enum RISCVException {
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
- RISCV_EXCP_SEMIHOST = 0x10,
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+ RISCV_EXCP_SEMIHOST = 0x3f,
} RISCVException;
#define RISCV_EXCP_INT_FLAG 0x80000000
--
2.45.1
- [PULL v2 00/27] riscv-to-apply queue, Alistair Francis, 2024/06/03
- [PULL v2 02/27] target/riscv/kvm: Fix exposure of Zkr, Alistair Francis, 2024/06/03
- [PULL v2 01/27] hw/intc/riscv_aplic: APLICs should add child earlier than realize, Alistair Francis, 2024/06/03
- [PULL v2 04/27] target/riscv/kvm: implement SBI debug console (DBCN) calls, Alistair Francis, 2024/06/03
- [PULL v2 06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63,
Alistair Francis <=
- [PULL v2 05/27] hw/riscv/boot.c: Support 64-bit address for initrd, Alistair Francis, 2024/06/03
- [PULL v2 03/27] target/riscv: Raise exceptions on wrs.nto, Alistair Francis, 2024/06/03
- [PULL v2 07/27] target/riscv/kvm: tolerate KVM disable ext errors, Alistair Francis, 2024/06/03
- [PULL v2 08/27] target/riscv/debug: set tval=pc in breakpoint exceptions, Alistair Francis, 2024/06/03
- [PULL v2 11/27] target/riscv: Add support for Zve64x extension, Alistair Francis, 2024/06/03
- [PULL v2 10/27] target/riscv: Add support for Zve32x extension, Alistair Francis, 2024/06/03
- [PULL v2 12/27] target/riscv: Relax vector register check in RISCV gdbstub, Alistair Francis, 2024/06/03
- [PULL v2 14/27] target/riscv/cpu.c: fix Zvkb extension config, Alistair Francis, 2024/06/03
- [PULL v2 15/27] target/riscv: Implement dynamic establishment of custom decoder, Alistair Francis, 2024/06/03
- [PULL v2 13/27] target/riscv: Fix the element agnostic function problem, Alistair Francis, 2024/06/03